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A hardware based implementation [chapter]

Roel Martínez, László Szirmay-Kalos, Mateu Sbert
2002 Advances in Modelling, Animation and Rendering  
This paper presents a depth buffer hardware implementation of the multipath algorithm for radiosity.  ...  The implementation makes use of bundles of parallel lines implemented with the OpenGL's depth buffer.  ...  The first shot step was implemented with local lines, although a hardware based implementation is also available in [14] . In this step were used 4 million local lines.  ... 
doi:10.1007/978-1-4471-0103-1_23 fatcat:celiptc6cfct5i2jpcyrzni5vm

Implementing hardware Trojans: Experiences from a hardware Trojan challenge

Georg T. Becker, Ashwin Lakshminarasimhan, Lang Lin, Sudheendra Srivathsa, Vikram B. Suresh, Wayne Burelson
2011 2011 IEEE 29th International Conference on Computer Design (ICCD)  
Hardware Trojans have become a growing concern in the design of secure integrated circuits.  ...  We introduced and implemented unique Trojans based on side-channel analysis that leak the secret key in the reference encryption algorithm.  ...  Implementation of hardware Trojans can be trigger-activated combinational or sequential circuits inserted at different abstraction levels.  ... 
doi:10.1109/iccd.2011.6081414 dblp:conf/iccd/BeckerLLSSB11 fatcat:dsg7ez5yabcbpghahsfa2yvgie

Hardware implementation of bluetooth security

P. Kitsos, N. Sklavos, K. Papadomanolakis, O. Koufopavlou
2003 IEEE pervasive computing  
Most single-chip Bluetooth baseband implementations, which include a low-performance general-purpose processor, implement only the data encryption in hardware.  ...  However, in time-critical applications requiring a fast connection and in devices with processing constraints, implementing key generation and authentication in the hardware (rather than software) is also  ...  We can implement the security protocol in these hardware components.  ... 
doi:10.1109/mprv.2003.1186722 fatcat:n7bzzfazvfdrfdfjivx2h7dcwe

Improving SHA-2 Hardware Implementations [chapter]

Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis
2006 Lecture Notes in Computer Science  
This paper proposes a set of new techniques to improve the implementation of the SHA-2 hashing algorithm.  ...  These techniques consist mostly in operation rescheduling and hardware reutilization, allowing a significant reduction of the critical path while the required area also decreases.  ...  Thus the critical path of the resulting hardware implementation can be reduced.  ... 
doi:10.1007/11894063_24 fatcat:2zww2wevg5aerjhpt4jsmpscmi

Fast Smith-Waterman hardware implementation

Zubair Nawaz, Koen Bertels, H. Ekin Sumbul
2010 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW)  
Keywords-computational biology; sequence alignment; hardware acceleration; RVE 1 This work is sponsored by the hArtes (IST-035143), the MORPHEUS (IST-027342) and RCOSY (DES-6392) projects.  ...  With the growing size of the sequence database, there is always a need for even faster implementation of SW.  ...  Table I RESULTS I TO SHOW TIME AND HARDWARE Type Implementation Frequency (MHz.)  ... 
doi:10.1109/ipdpsw.2010.5470748 dblp:conf/ipps/NawazBS10 fatcat:lnsdtp6ozfb5jk7jmodyhzhcie

XTR Implementation on Reconfigurable Hardware [chapter]

Eric Peeters, Michael Neve, Mathieu Ciet
2004 Lecture Notes in Computer Science  
We also compare our implementations with hardware implementations of RSA and ECC.  ...  In this paper, we are dealing with hardware implementation of XTR, and more precisely with Field Programmable Gate Array (FPGA).  ...  One of our purposes for implementing XTR architectures on reconfigurable hardware is to achieve a well-balanced trade-off between hardware size and frequency.  ... 
doi:10.1007/978-3-540-28632-5_28 fatcat:z4vw3quxkfhxzlqclf5q6nwbty

Hardware Implementation of Hash Functions [chapter]

Zhijie Shi, Chujiao Ma, Jordan Cote, Bing Wang
2011 Introduction to Hardware Security and Trust  
Implementation of Hash Functions Hardware Implementation of Hash Functions Hardware Implementation of Hash Functions Hardware Implementation of Hash Functions Hardware Implementation  ...  of Hash Functions Hardware Implementation of Hash Functions Hardware Implementation of Hash Functions Hardware Implementation of Hash Functions Hardware Implementation of Hash Functions  ... 
doi:10.1007/978-1-4419-8080-9_2 fatcat:cgxyrhty2jcrbaaknstb5b4vh4

Implementation of hardware genetic algorithm

Imbaby Mahmoud, May Salama, Asmaa Abdel Tawab
2008 The International Conference on Electrical Engineering  
This work presents a hardware implementation of a Genetic Algorithm. Hardware Genetic Operators are implemented in FPGA.  ...  Fitness evaluation, which is problem dependent, is left for implementation as S/W module or problem specific hardware design.  ...  This allows a mixed hardware/software approach to address both generality and acceleration. In some cases the fitness evaluation can be simplified implemented in H/W.  ... 
doi:10.21608/iceeng.2008.34332 fatcat:ucnqxshkazgh7kenkdih4zltne

Implementing decision trees in hardware

J.R. Struharik
2011 2011 IEEE 9th International Symposium on Intelligent Systems and Informatics  
Proposed hardware architectures are suitable for the implementation in both Field Programmable Gate Arrays (FPGA) and Application Specific Integrated Circuits (ASIC).  ...  In this paper several hardware implementations of decision trees (axis-parallel, oblique and non-linear) based on the concept of universal node and sequence of universal nodes are presented.  ...  classification time per instance for hardware DT implementation.  ... 
doi:10.1109/sisy.2011.6034358 fatcat:d5t6loeag5ewvoh5kux3w5tek4

Hardware Implementation of Fuzzy Controllers [chapter]

Victor Varshavsky, Viacheslav Marakhovsky, Ilya Levin, Hiroshi Saito
2011 Fuzzy Controllers, Theory and Applications  
Hardware Implementation of Fuzzy Controllers, Fuzzy Controllers, Theory and Applications, Dr.  ...  This methodology is oriented to hardware implementation of fuzzy controllers as analog devices.  ... 
doi:10.5772/13414 fatcat:jonbn2hrffeale535ghpsrc4mq

Hardware implementation of recursive algorithms

Dmitri Mihhailov, Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson
2010 2010 53rd IEEE International Midwest Symposium on Circuits and Systems  
of recursive sorting algorithms compared to known implementations both in hardware and in software.  ...  The paper presents new results in the hardware implementation and optimization of recursive sequential and parallel algorithms using the known and a new model of a hierarchical finite state machine.  ...  It has been shown [2] however that recursion can be implemented much more efficiently in hardware.  ... 
doi:10.1109/mwscas.2010.5548674 fatcat:wft566tfwbg63m2ecqtwa5og6u

Recurrent Neural Networks Hardware Implementation on FPGA [article]

Andre Xian Ming Chang, Berin Martini, Eugenio Culurciello
2016 arXiv   pre-print
We implemented a RNN with 2 layers and 128 hidden units in hardware and it has been tested using a character level language model.  ...  In this paper we present a hardware implementation of Long-Short Term Memory (LSTM) recurrent network on the programmable logic Zynq 7020 FPGA from Xilinx.  ...  We would like to thank Vinayak Gokhale for the discussion on implementation and hardware architecture and also thank Alfredo Canziani, Aysegul Dundar and Jonghoon Jin for the support.  ... 
arXiv:1511.05552v4 fatcat:dpav4x43hjab7e3vvuu6pl362e

Hardware Implementation of Fano Decoder for Polarization-adjusted Convolutional (PAC) Codes [article]

Amir Mozammel
2021 arXiv   pre-print
This brief proposes a hardware implementation architecture for Fano decoding of polarization-adjusted convolutional (PAC) codes.  ...  of sequential decoding for PAC codes has never been studied from a hardware implementation perspective.  ...  Whenever the Fano decoder moves forward, Fig. 5 . 5 Hardware implementation of Table I (metric calculator).  ... 
arXiv:2011.09819v3 fatcat:et2eumdd5bh37dli7ccgmf5pxe


Vit Fabera, Tomas Musil, Jakub Rada
2017 Neural Network World  
This paper describes the first attempt of hardware implementation of Multistream Compression (MSC) algorithm.  ...  Those state machines are then implemented in VHDL to selected FPGA platform. The algorithm utilizes a special tree data structure, called MSC tree.  ...  This paper focuses on the implementation details of the algorithm in hardware. Implementation overview The described hardware implementation was built using RTL methodology as describe in [6] .  ... 
doi:10.14311/nnw.2017.27.029 fatcat:jtmalx3az5by7j7ggd66n5blt4

Hardware implementation of smart antenna systems

H. Wang, M. Glesner
2006 Advances in Radio Science  
Design of smart antenna systems combines the technologies of antenna design, signal processing, and hardware implementation.  ...  In this paper, a propose of smart antenna structure, as well as some function blocks that have been already implemented in hardware will be presented.</p>  ...  implementation items, and there is a conclusion at the end.  ... 
doi:10.5194/ars-4-185-2006 fatcat:huwjqqnoczdyri2tz625tre7mm
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