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eXtended block cache

S. Jourdan, L. Rappoport, Y. Almog, M. Erez, A. Yoaz, R. Ronen
Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550)  
This paper describes a new instruction-supply mechanism, called the eXtended Block Cache (XBC). The goal of the XBC is to improve on the Trace Cache (TC) hit rate, while providing the same bandwidth.  ...  The basic unit recorded in the XBC is the extended block (XB), which is a multiple-entry single-exit instruction block.  ...  In order to achieve this goal, we design a new frontend structure, called the eXtended Block Cache (XBC).  ... 
doi:10.1109/hpca.2000.824339 dblp:conf/hpca/JourdanRAEYR00 fatcat:hjn3u2mtirhjzm7nlpkjbz3uqy

Performance estimation of multiple-cache IP-based systems

Sungjoo Yoo, Kyoungseok Rha, Youngchul Cho, Jinyong Jung, Kiyoung Choi
2000 Proceedings of the eighth international workshop on Hardware/software codesign - CODES '00  
In the case study with a ½ Even a single cache can have several parameters such as cache size, associativity, block (line) size, sub-block size, replacement policy, etc.  ...  architecture with an extended shared memory model.  ...  Figure 7 : 7 Pseudo code of the extended shared memory model. Victim block state is the state of victim cache block to be replaced by the memory access.  ... 
doi:10.1145/334012.334027 dblp:conf/codes/YooRCJC00 fatcat:htxbanu65jhath2ipa2yhh2oda

Improving Cloud System Performances by Adopting Nvram-Based Storage Systems

Jisun Kim, Yunjoo Park, Sunhwa A Nam, Hyunkyoung Choi, KyungWoon Cho, Hyokyung Bahn
2016 International Journal of Natural Sciences Research  
It can also be utilized as swap or journal devices if we use it as a block I/O device.  ...  We first consider NVRAM as an additional storage cache and show how much performance improvement can be obtained if we adopt NVRAM cache.  ...  Writes to secondary storage occurs only when a block is removed from the nonvolatile cache. Also, we assume that all clean blocks reside in volatile cache.  ... 
doi:10.18488/journal.63/2016.4.6/63.6.100.106 fatcat:susdlad3ubacvcydxz3y64wpdq

Modeled and measured instruction fetching performance for superscalar microprocessors

S. Wallace, N. Bagherzadeh
1998 IEEE Transactions on Parallel and Distributed Systems  
We d e v elop a mathematical model for three di erent cache techniques and evaluate its performance both in theory and in simulation using the SPEC95 suite of benchmarks.  ...  Extended Cache The probability the starting address in the block is at position i for the extended cache is With the cache line size extended beyond the desired n instructions, if there is a control transfer  ...  Figure 14 shows the expected instruction fetch for the simple cache, extended cache, and self-aligned cache for dual block fetching with prefetching.  ... 
doi:10.1109/71.689444 fatcat:pubbhujplbbgvhl3fyn2wza33q

Instruction fetching mechanisms for superscalar microprocessors [chapter]

Steven Wallace, Nader Bagherzadeh
1996 Lecture Notes in Computer Science  
Figure 3 shows the expected instruction fetch for the simple cache, extended cache, and self-aligned cache with prefetching for b = 1=8, n = 8, q = p + n, and m = 2 q (extended only) verses p.  ...  Three di erent c a c he options are then brie y described: a simple cache type, an extended cache type, and a self-aligned cache type.  ... 
doi:10.1007/bfb0024773 fatcat:tbvcapcxxbfghdec7sgslq2u7u

Dynamic Tag-Check Omission: A Low Power Instruction Cache Architecture Exploiting Execution Footprints [chapter]

Koji Inoue, Vasily Moshnyaga, Kazuaki Murakami
2003 Lecture Notes in Computer Science  
Execution footprints are recorded in an extended BTB (Branch Target Buffer), and are used to know the cache residence of target instructions before starting cache access.  ...  This paper proposes an architecture for low-power direct-mapped instruction caches, called "history-based tag-comparison (HBTC) cache".  ...  When an instruction block is referenced without causing any cache miss, a corresponding execution footprint is recorded in an extended BTB (Branch Target Buffer).  ... 
doi:10.1007/3-540-36612-1_2 fatcat:mclyh4aqkzd3ppbklduhyifalu

A Comprehensive Analytical Performance Model of DRAM Caches

Nagendra Gulur, Mahesh Mehendale, Ramaswamy Govindarajan
2015 Proceedings of the 6th ACM/SPEC International Conference on Performance Engineering - ICPE '15  
and L Mem . • Larger block sizes can capture spatial locality. • Bandwidth-neutral model: Cache miss rate halves with doubling of cache block size. » If this holds, then measuring hit rate at smallest  ...  block size via trace based analysis is sufficient. » For larger block sizes, estimate via:• Row-Buffer Hit rate (RBH) of the DRAM cache depends on the access pattern and the data organization on the DRAM  ... 
doi:10.1145/2668930.2688044 dblp:conf/wosp/GulurMG15 fatcat:dd737ec5tfau5ihlwbgd5xtbye

Preventing Fast Wear-out of Flash Cache with An Admission Control Policy

Eunji Lee, Hyokyung Bahn
2015 JSTS Journal of Semiconductor Technology and Science  
Second, more than 50% of data has no hit in flash cache as it is a second level cache.  ...  Based on these observations, we propose a cache admission control policy that does not cache data when it is first accessed, and inserts it into the cache only after its second access occurs within a certain  ...  In this algorithm, blocks referenced only once are quickly removed from the cache, while blocks that are repeatedly referenced can remain in the buffer cache for an extended period of time.  ... 
doi:10.5573/jsts.2015.15.5.546 fatcat:2x46ykpbdfgvnl47otglmlynn4

Vlsi Design of Cache Compression in Microprocessor Using Pattern Matching Technique

M. Nisha Angeline
2012 IOSR Journal of Electronics and Communication Engineering  
By this method the speed and the power can be improved without affecting the performance of system cache.  ...  Accessing off-chip memory takes an order of magnitude more time than accessing an on-chip cache, two orders of magnitude more time than executing an instruction.  ...  The AWN technique is extended by providing some additional space for the upper half-word AHS of a few normal-sized words in a cache block, with an aim to convert them into narrow blocks.  ... 
doi:10.9790/2834-0163137 fatcat:vdg7elehyrb4lk6ox6z3tln7zq

Impact of Extending Side Channel Attack on Cipher Variants: A Case Study with the HC Series of Stream Ciphers [chapter]

Goutam Paul, Shashwat Raizada
2012 Lecture Notes in Computer Science  
Cache management in modern processors divides the available cache memory into blocks of b bytes. For a given block, all the b bytes must be loaded together.  ...  Cache with block size b bytes holds b/4 array words, the cache blocks can be numbered using the first 8 − log 2 (b/4) bits. For each call, two elements of the array are accessed.  ...  Cache Analysis Attacks (contd.) To ensure consistency between the data in the RAM and the cache, a record of cache blocks being loaded into the cache is maintained.  ... 
doi:10.1007/978-3-642-34416-9_3 fatcat:rg4qax4ggnddrambcjt6zvt5sq

Investigating optimal local memory performance

Olivier Temam
1998 SIGPLAN notices  
Recent work has demonstrated that, cache space is often poorly utilized.  ...  However, no previous work has yet demonstrated upper bounds on what a cache or local memory could achieve when exploiting both spatial and temporal locality. Belady's MIN al-  ...  , intermediate between CACHE and EXTENDED BELADY and we outline the limitations of the cache line paradigm.  ... 
doi:10.1145/291006.291050 fatcat:hvt6qy7kvvfubb7hn5strhqwje

Improving Flash-Based Disk Cache with Lazy Adaptive Replacement

Sai Huang, Qingsong Wei, Dan Feng, Jianxi Chen, Cheng Chen
2016 ACM Transactions on Storage  
LARC can filter out seldom accessed blocks and prevent them from entering cache. This avoids cache pollution and keeps popular blocks in cache for a longer period of time, leading to higher hit rate.  ...  In this way, LARC improves performance and extends SSD lifetime at the same time. LARC is self-tuning and low overhead.  ...  They also introduced a seive mechnism which only allocates cache space for blocks on their n th access. It reduces allocation writes to SSD and thus extends it lifetime.  ... 
doi:10.1145/2737832 fatcat:dbr5t35j4rgxpgto3gqd2vhkpi

Improving flash-based disk cache with Lazy Adaptive Replacement

Sai Huang, Qingsong Wei, Jianxi Chen, Cheng Chen, Dan Feng
2013 2013 IEEE 29th Symposium on Mass Storage Systems and Technologies (MSST)  
LARC can filter out seldom accessed blocks and prevent them from entering cache. This avoids cache pollution and keeps popular blocks in cache for a longer period of time, leading to higher hit rate.  ...  In this way, LARC improves performance and extends SSD lifetime at the same time. LARC is self-tuning and low overhead.  ...  They also introduced a seive mechnism which only allocates cache space for blocks on their n th access. It reduces allocation writes to SSD and thus extends it lifetime.  ... 
doi:10.1109/msst.2013.6558447 dblp:conf/mss/HuangWCCF13 fatcat:ygc245mg5ze4xmxuokvlwvav3a

Investigating optimal local memory performance

Olivier Temam
1998 Proceedings of the eighth international conference on Architectural support for programming languages and operating systems - ASPLOS-VIII  
Recent work has demonstrated that, cache space is often poorly utilized.  ...  However, no previous work has yet demonstrated upper bounds on what a cache or local memory could achieve when exploiting both spatial and temporal locality. Belady's MIN al-  ...  , intermediate between CACHE and EXTENDED BELADY and we outline the limitations of the cache line paradigm.  ... 
doi:10.1145/291069.291050 dblp:conf/asplos/Temam98 fatcat:ja6gjtjj2rawph6bbyg3xwkq2m

Investigating optimal local memory performance

Olivier Temam
1998 ACM SIGOPS Operating Systems Review  
Recent work has demonstrated that, cache space is often poorly utilized.  ...  However, no previous work has yet demonstrated upper bounds on what a cache or local memory could achieve when exploiting both spatial and temporal locality. Belady's MIN al-  ...  , intermediate between CACHE and EXTENDED BELADY and we outline the limitations of the cache line paradigm.  ... 
doi:10.1145/384265.291050 fatcat:hi5gs7nuobai3jzbyenbcycrx4
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