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Worst-Case Reaction Time Optimization on Deterministic Multi-Core Architectures with Synchronous Languages

Nicolas Hili, Alain Girault, Eric Jenn
2019 2019 IEEE 25th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)  
Our approach is based on the execution of synchronous programs written in the ForeC programming language on deterministic architectures called PREcision Timed.  ...  In this paper, we propose a new approach for the predictability and optimality of the inter-core communication and execution of tasks allocated on different cores of multicore architectures.  ...  Finding the longest computation results in finding the Worst-Case Reaction Time (WCRT) of the system.  ... 
doi:10.1109/rtcsa.2019.8864570 dblp:conf/rtcsa/HiliGJ19 fatcat:3bjl2hrccbb7jbew7j64kf3iqi

Faster Function Blocks for Precision Timed Industrial Automation

Hammond Pearce, Partha Roop, Morteza Biglari-Abhari, Martin Schoeberl
2018 2018 IEEE 21st International Symposium on Real-Time Distributed Computing (ISORC)  
Overall, our improvements resulted in 60% shorter worst-case execution times.  ...  In this paper, we examine how the performance of synchronous IEC 61499 can be improved through the usage of the multi-core T-CREST architecture, data scratchpads, and an optimised compiler.  ...  The optimised approach, using the four-core architecture, goFB, and SPMs, proved to have 60 % lower statically analysed Worst-Case Reaction Times (on average) than FBC running on a single-core Patmos.  ... 
doi:10.1109/isorc.2018.00017 dblp:conf/isorc/PearceRBS18 fatcat:oqpixuxqp5cyrc77ntoy53tjlu

The Logical Execution Time Paradigm: New Perspectives for Multicore Systems (Dagstuhl Seminar 18092)

Rolf Ernst, Stefan Kuntz, Sophie Quinton, Martin Simons, Michael Wagner
2018 Dagstuhl Reports  
(LET) abstraction, which was originally introduced as a realtime programming paradigm, has gained traction recently in the automotive industry with the shift to multicore architectures.  ...  LET abstracts from the actual timing behavior of real-time tasks on the physical platform: Independent of when a task executes, the time interval between its reading input and writing output is fixed by  ...  That is, without a proper synchronization mechanism, in the worst-case the memory accesses issued by one core can interfere with the other, and viceversa, leaving room for pathological scenarios that inevitably  ... 
doi:10.4230/dagrep.8.2.122 dblp:journals/dagstuhl-reports/ErnstKQS18 fatcat:6k7z4uyijrhuxceulih3jeiqoa

Scade 6: From a Kahn Semantics to a Kahn Implementation for Multicore

Jean-Louis Colaco, Bruno Pagano, Cedric Pasteur, Marc Pouzet
2018 2018 Forum on Specification & Design Languages (FDL)  
One ongoing work is the generation of code for multi-core architectures.  ...  inspired from Lucid Synchrone.  ...  And when implementing on a multi-core it is not necessary to know what the pieces of code to integrate are computing but only timing aspects (worst-case execution time, worst-case communication time) to  ... 
doi:10.1109/fdl.2018.8524052 dblp:conf/fdl/ColacoPPP18 fatcat:qkirynzfkzafternidprmxa55e

Programming and Timing Analysis of Parallel Programs on Multicores

Eugene Yip, Partha S. Roop, Morteza Biglari-Abhari, Alain Girault
2013 2013 13th International Conference on Application of Concurrency to System Design  
ForeC extends C with a minimal set of constructs adopted from synchronous languages.  ...  This paper proposes the ForeC language for the deterministic parallel programming of embedded applications on multicores.  ...  This is known as the worst-case reaction time (WCRT) analysis [15] .  ... 
doi:10.1109/acsd.2013.19 dblp:conf/acsd/YipRBG13 fatcat:d6dc57b3nvfafm62bjarkgkkly

Adaptive Isolation for Predictability and Security (Dagstuhl Seminar 16441)

Tulika Mitra, Jürgen Teich, Lothar Thiele, Marc Herbstritt
2017 Dagstuhl Reports  
Semiconductor technology is at the verge of integrating hundreds of processor cores on a single device. Indeed, affordable multi-processor system-on-achip (MPSoC) technology is becoming available.  ...  Instead of best-effort and average performance, these real-time applications demand timing predictability and/or security levels specifiable on a per-application basis.  ...  Acknowledgements We would like to take the opportunity to thank and acknowledge our organization team member Ingrid Verbauwhede for her great effort in contributing brilliant ideas and suggestions on the  ... 
doi:10.4230/dagrep.6.10.120 dblp:journals/dagstuhl-reports/MitraTT16 fatcat:xvvcpukdp5ftrfeiz5ar5xksse

Optimal Implementation of Simulink Models on Multicore Architectures with Partitioned Fixed Priority Scheduling

Shamit Bansal, Yecheng Zhao, Haibo Zeng, Kehua Yang
2018 2018 IEEE Real-Time Systems Symposium (RTSS)  
However, the current research on software synthesis for Simulink models has a critical gap for providing a deterministic, semantics-preserving implementation on multicore architectures with partitioned  ...  model semantics, and to optimize the control performance.  ...  Reactive UD Unit Delay WCET Worst Case Execution Time WCRT Worst Case Response Time xii Figure 1.1: Determinism in concurrent SR Models, such that black arrow represents trigger of task, dotted  ... 
doi:10.1109/rtss.2018.00041 dblp:conf/rtss/BansalZZY18 fatcat:p532mmn5gfajvml2tpbh6w4v2e

Exploring system architectures in AADL via Polychrony and SynDEx

Huafeng Yu, Yue Ma, Thierry Gautier, Loïc Besnard, Jean-Pierre Talpin, Paul Le Guernic, Yves Sorel
2013 Frontiers of Computer Science  
However, little work takes code distribution and architecture exploration into account, particularly considering clock constraints, for distributed multi-processor systems.  ...  Architecture analysis & design language (AADL) has been increasingly adopted in the design of embedded systems, and corresponding scheduling and formal verification have been well studied.  ...  the real-time characteristics (worst case execution time (WCET), worst case communication time (WCCT) Fig. 4 4 A time model of the execution of a thread Fig. 5 5 In event data port translation next  ... 
doi:10.1007/s11704-013-2307-z fatcat:ytsuc3zkkfhsddwczpiiglfs2i

Programmable Logic Controllers in the Context of Industry 4.0

Martin A. Sehr, Marten Lohstroh, Mathew Weber, Ines Ugalde, Martin Witte, Joerg Neidig, Stephan Hoeme, Mehrdad Niknami, Edward A. Lee
2020 IEEE Transactions on Industrial Informatics  
Specifically, we propose deterministic, distributed programming models that embrace explicit timing, eventtriggered computation, and improved security.  ...  Any event that is handled by a cyclic task with period T has a worst-case response time of at least T .  ...  Moreover, in a safety-critical system, we have to validate the behavior of the system under worst-case timing conditions, so we have to design the system to work with worst-case delays anyway.  ... 
doi:10.1109/tii.2020.3007764 fatcat:oso5q4ysine7fhojlzo3uuq4ya

Synchronous Programming (Dagstuhl Seminar 13471)

Stephen A. Edwards, Alain Girault, Klaus Schneider, Marc Herbstritt
2014 Dagstuhl Reports  
Synchronous programming languages are programming languages with an abstract (logical) notion of time: The execution of such programs is divided into discrete reaction steps, and in each of these reactions  ...  The programs are called synchronous because all outputs are computed together in zero time within a step and because parallel components synchronize their reaction steps by the semantics of the languages  ...  We briefly present a problem posed to use by Rafel Cases and Jordi Cortadella during a lunch organised by Gerard Berry. We propose solutions in the Simulink tool 3 and our language Zélus 4 .  ... 
doi:10.4230/dagrep.3.11.117 dblp:journals/dagstuhl-reports/EdwardsGS13 fatcat:b7aq6w2q4fawjjqtlfleujr3gi

A GALS Language for Dynamic Distributed and Reactive Programs

Avinash Malik, Alain Girault, Zoran Salcic
2011 2011 Eleventh International Conference on Application of Concurrency to System Design  
We propose a Globally Asynchronous Locally Synchronous language DSystemJ for designing dynamic distributed systems.  ...  DSystemJ, an extension of the reactive asynchronous SystemJ language, enhances it with dynamic creation and process mobility, and uses the Java language for programming sequential data computations.  ...  The model-checking approach described in the previous point can also be utilized for Worst Case Reaction Time (WCRT) analysis.  ... 
doi:10.1109/acsd.2011.30 dblp:conf/acsd/MalikGS11 fatcat:a5n4e4ojonhbxn444u3swah6re

Response time analysis of dataflow applications on a many-core processor with shared-memory and network-on-chip

Amaury Graillat, Claire Maiza, Matthieu Moy, Pascal Raymond, Benoît Dupont de Dinechin
2019 Proceedings of the 27th International Conference on Real-Time Networks and Systems - RTNS '19  
We consider hard real-time applications running on many-core processor containing several clusters of cores linked by a Network-on-Chip (NoC).  ...  This schedule guarantees that deadlines are met, and therefore provides a safe upper bound to the global worst-case response time.  ...  Since we consider hard real-time applications, we optimize the application and analysis for the worst-case.  ... 
doi:10.1145/3356401.3356416 dblp:conf/rtns/GraillatMMRD19 fatcat:lqkuvpodcreltiesmb5kmsojaq

Optimizing the implementation of real-time Simulink models onto distributed automotive architectures

Gang Han, Marco Di Natale, Haibo Zeng, Xue Liu, Wenhua Dou
2013 Journal of systems architecture  
We provide a formulation of the FlexRay scheduling problem that computes the optimal solution with respect to the number of additional delays when a flow-preserving implementation is not possible.  ...  The aforementioned scheduling options are applied to an X-by-wire system and a case study with active-safety functions to highlight tradeoffs between schedulability and additional functional delays.  ...  The algorithm assumes that nodes are synchronized, with an architecture similar to the one discussed in this work.  ... 
doi:10.1016/j.sysarc.2013.08.009 fatcat:cnsznfvg4nclthqb2rvfurasne

Sheep in wolf's Clothing: Implementation Models for Dataflow Multi-Threaded Software

Keryan Didier, Albert Cohen, Dumitru Potop-Butucaru, Adrien Gauffriau
2019 2019 19th International Conference on Application of Concurrency to System Design (ACSD)  
We show applicability on a large-scale industrial avionics case study and on a commercial many-core.  ...  Fortunately, it is often the case that multi-threaded, semaphore-synchronized embedded software implements high-level functional specifications written in a deterministic data-flow language such as Scade  ...  Acknowledgments The authors would like to thank Xavier Leroy, François Irigoin, and Jean Souyris for having provided significant feedback on early versions of this work.  ... 
doi:10.1109/acsd.2019.00009 dblp:conf/acsd/DidierCPG19 fatcat:s44hunmpxzgpbksyjuazw2nejm

Asynchronous on-chip networks

M. Amde, T. Felicijan, A. Efthymiou, D. Edwards, L. Lavagno
2005 IEE Proceedings - Computers and digital Techniques  
They can provide a solution for low power consumption in chips and simplify global timing assumptions, e.g. on clock skew, by having asynchronous communication between modules.  ...  A few methodologies, including globally asynchronous, locally synchronous and desynchronisation, aim at leveraging the benefits of both synchronous and asynchronous design paradigms.  ...  Worst case performance: The circuit always designed for the worst-case performance, since the critical path in the circuit determines the clock period. .  ... 
doi:10.1049/ip-cdt:20045093 fatcat:jedytsssjfcmjoyrajrn47ue6e
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