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Wormhole run-time reconfiguration
1997
Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays - FPGA '97
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Wormhole Run-time Reconfiguration is presented as a distributed control methodology that is applicable not only to the problem of device-level CCM reconfiguration, but to system-wide concurrent computing ...
For an efficient platform, the swapping of the computational hardware (referred to as Run-Time Reconfiguration, or RTR) must be rapid. ...
run-time reconfigurable CCM platforms. ...
doi:10.1145/258305.258315
dblp:conf/fpga/BittnerA97
fatcat:xtrobdsjozenrcsbuukpuov4gu
Colt: an experiment in wormhole run-time reconfiguration
1996
High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic
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Wormhole Run-Time Reconfiguration (RTR) is an attempt to create an refined computing paradigm for high performance computational tasks. ...
reconfiguration. ...
Athanas, "Stream-Based Processing Using Wormhole Run-time Reconfiguration," in preparation. ...
doi:10.1117/12.255815
fatcat:zdxstrsirzhhnhfl37kfw7uxs4
Design Optimizations for Tiled Partially Reconfigurable Systems
2011
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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We propose a design method for selecting suitable synthesis regions for the PR modules aiming to optimize their placement at run-time. ). J. Hagemeyer and M. ...
In partially reconfigurable architectures, system components can be dynamically loaded and unloaded allowing resources to be shared over time. ...
Since every PR module uses the same resources for the embedded macro, the macro is not modified at the run-time reconfiguration of a PR module. ...
doi:10.1109/tvlsi.2010.2044902
fatcat:etom2d2dy5hmbczyyrrfnvuy3a
Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs
[chapter]
2002
Lecture Notes in Computer Science
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To this end, we are investigating reconfigurable architectures, composed of an instruction-set processor running software processes and coupled to an FPGA on which hardware tasks are spawned by dynamic ...
partial reconfiguration. ...
Therefore, there is no need for complex run-time circuit re-routing as required in previous works [5] and circuit integrity is guaranteed. ...
doi:10.1007/3-540-46117-5_82
fatcat:qcf7thcrmjf5pdoqukd6yzduku
DBR: A Simple, Fast and Efficient Dynamic Network Reconfiguration Mechanism Based on Deadlock Recovery Scheme
2012
International Journal of VLSI Design & Communication Systems
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Dynamic network reconfiguration is described as the process of replacing one routing function with another while the network keeps running. ...
The mechanism which is referred to as DBR guarantees a deadlock-free reconfiguration based on wormhole switching (WS) and it does not require additional resources. ...
On the other hand, traces are based on capturing the traffic when running real applications. Traces contain the source, destination, injection time and the size of each sent message. ...
doi:10.5121/vlsic.2012.3502
fatcat:g2dgdjpkunf7zkmxjrfim3u2xm
Energy Optimised Security against Wormhole Attack in IoT-Based Wireless Sensor Networks
2021
Computers Materials & Continua
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In this paper, we developed the ESWI technique for detecting the wormhole attack while improving the performance and security. ...
During data sharing, security is an important concern in such networks as they are prone to many threats, of which the deadliest is the wormhole attack. ...
The detection algorithm is then run on the suspicious nodes, and the wormholes are detected by evaluating the hop-count time gap using the hop-time stamp. ...
doi:10.32604/cmc.2021.015259
fatcat:nmxuldn5ifaajkpa4bb5msh5qi
An FPGA-Based Dynamically Reconfigurable Platform: From Concept to Realization
2006
2006 International Conference on Field Programmable Logic and Applications
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Using partial dynamic reconfiguration allows the main system to run uninterrupted during the reconfiguration process in addition to the reduced time for the reconfiguration process. ...
Dynamically reconfigurable FPGA-based systems offer a new kind of flexibility such as on-demand computing, self-adaption and self-optimization capabilities by restructuring the hardware at run-time. ...
This flexibility allows to place application modules at run-time in any available slot regardless of any I/O requirements. ...
doi:10.1109/fpl.2006.311364
dblp:conf/fpl/Majer06
fatcat:eunextuzuje3ld3flhgua6rv3m
Uncertainty and Predictability: Can They Be Reconciled?
[chapter]
2003
Lecture Notes in Computer Science
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properties would ensure predictable (timely and secure) management and reconfiguration of the ON. ...
The Timely Computing Base can for example be used to build perfect failure detectors and thus support asynchronous algorithms running on the payload system and relying on the former detectors[1.7]. ...
doi:10.1007/3-540-37795-6_20
fatcat:fltxsb3agncnlnrtr7z4j4jydu
Table of Contents
2007
2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP)
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.............................................. 186 A Triplet Based Computer Architecture Supporting Parallel Ohject Computing .................. 192 The Design of a Novel Object Processor: OOMIPS 108 Run-Time ...
Computing .........174 SIMD Vectorization of Histogram Functions ................................. 174 A Run-Time Reconfigurahle Fahric for 3D Texture Filteri'ng ............................ 180 Reconfigurahle ...
doi:10.1109/asap.2007.4429950
fatcat:4vmskttnbfdfxblzuug25tjgzu
Path Concepts for a Reconfigurable Bit-Serial Synchronous Architecture
[chapter]
2005
Lecture Notes in Computer Science
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This paper develops path concepts for the execution of different algorithms on a reconfigurable architecture. ...
The application specificity of the basic version of the architecture can be overcome by so called routers, achieving a reconfigurable system. ...
The concept of wormhole run time reconfiguration [7] relies on a distributed control scheme and therefore avoids central controllers. ...
doi:10.1007/11596356_46
fatcat:46g6oqboknahtbmnvzrl43btx4
Supercomputer Supernet (SSN): a high-speed electro-optic campus and metropolitan network
1996
Optical Interconnects in Broadband Switching Architectures
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The WDM oplical backbone extends the geographic coverage range from inerdepartmenal io campus and even o mefropol2an areas w2h dynamically reconfigurable direct or muUi-hop connections. ...
The Supercomputer Supernel (SSN} is a highperformance, scalable optical interconnection nelwork I or supercompulers and worksaiion cMsers based on asynchronous, wormhole-rouing switches. ...
Running over the existing dark fiber, SSN would provide four times the capacity (3.2 Gbit/s) and lower latency routing between the two
Figure 7 : 7 Figure 7: SSN supports a fine-grain distributed supercomputing ...
doi:10.1117/12.235857
fatcat:qji7cuctm5etpi7nxqp2no2x3q
Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC
2006
First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)
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time, thus aiming to provide low latency, low power and high data throughput. ...
This paper describes the architecture of our dynamically reconfigurable Network-on-Chip (NoC) architecture that has been proposed for reconfigurable Multiprocessor system-on-chip (MPSoC), as a solution ...
[8] propose a hybrid switching scheme that dynamically combines both virtual cut-through and wormhole switching to provide higher achievable throughput values compared to wormhole switching alone. ...
doi:10.1109/ahs.2006.25
dblp:conf/ahs/AhmadEK06
fatcat:rqombt4tgvcdxe27uuu6jvhoue
A Survey Article on Wormhole Attack Detection and Security in Wireless Sensor Networks
2017
International Journal of Computer Applications
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Simulators ultimate effects demonstrate that pretty much every wormhole is available and also remote in very a quick time period greater than a huge selection of scenarios. ...
Our own selection permits finding of one's wormhole, with rural location of one's harmful nodes. ...
Evidence of a link i harr j runs in two phases. In the rendezvous period, the nodes change nonce's alpha i and beta j . ...
doi:10.5120/ijca2017915666
fatcat:dxwcongk55gkfldozsxp5vvjm4
Design of a HW/SW communication infrastructure for a heterogeneous reconfigurable processor
2008
Proceedings of the conference on Design, automation and test in Europe - DATE '08
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Exploiting run-time adaptivity opens a new area of research by considering dynamic reconfiguration. ...
On a reference CMOS090 implementation the described interconnect system works at the system reference frequency of 200 MHZ sustaining the required run-time bandwidth on a set of reference applications, ...
Word or sub-word oriented Run-time Reconfigurable Architectures (RAs) [1] offer highly parallel, scalable solutions combining hardware performance with software flexibility. ...
doi:10.1145/1403375.1403700
fatcat:5zby5nhhtrefda7hw7fwrljo6q
Threat Adaptive Byzantine Fault Tolerant State-Machine Replication
2021
2021 40th International Symposium on Reliable Distributed Systems (SRDS)
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ThreatAdaptive avoids this pitfall by proactively preparing the reconfiguration that may be triggered by an increasing threat when it optimizes its performance. ...
Since replicas typically communicate with each other using an asynchronous network they cannot rely on consensus to decide how the system should be reconfigured. ...
However, such a time synchronized response introduces significant complexity and overhead in the threat detector wormhole. ...
doi:10.1109/srds53918.2021.00017
fatcat:ut23dqpk7ncyjhw6x6x3sndayy
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