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Validation of Hardware Security and Trust: A Survey [article]

Payman Behnam
2018 arXiv   pre-print
Then, we provide more details about various validation techniques for hardware security and trust.  ...  Many researchers all around the world come up with solutions to address various challenges that are crucial for industry and market.  ...  VERIFICATION TECHNIQUES FOR HARWARE TRSUT Generally, there are there categories for validation of hardware trust. They are functional, formal and trust verification approaches [51, 22] .  ... 
arXiv:1801.00649v1 fatcat:6eworcng6ndwbdanjnh2dlz2h4

Formalizing hardware/software interface specifications

Juncao Li, Fei Xie, Thomas Ball, Vladimir Levin, Con McGarvey
2011 2011 26th IEEE/ACM International Conference on Automated Software Engineering (ASE 2011)  
Although co-simulation and co-verification techniques have been utilized to facilitate the driver development, Hardware/Software (HW/SW) interface models, as the test harnesses, are often challenging to  ...  Software drivers are usually developed after hardware devices become available. This dependency can induce a long product cycle.  ...  For B, there are input symbols such as {wr_a}, {rd_a}, {no_evt} ∈ Σ, where the propositional variables wr_a and rd_a represent the software interface events when software writes/reads the hardware register  ... 
doi:10.1109/ase.2011.6100048 dblp:conf/kbse/LiXBLM11 fatcat:2iigidstfje43ed4kiptkm6744

PSL: Beyond Hardware Verification [chapter]

Ziv Glazberg, Mark Moulin, Avigail Orni, Sitvanit Ruah, Emmanuel Zarpas
2007 Next Generation Design and Verification Methodologies for Distributed Embedded Control Systems  
While PSL is mainly used for hardware verification, it can, in fact, be used to verify a wide variety of systems, including missile interception systems, railway interlocking protocols, system automation  ...  We discuss and exemplify how PSL can be used as a general purpose language for the specification of models and properties, beyond hardware systems.  ...  Acknowledgements The authors wish to thank Cindy Eisner for her helpful suggestions. References  ... 
doi:10.1007/978-1-4020-6254-4_19 fatcat:3e7vrrgtubgo5cdc5svcfepxhq

Hardware-software Codesign

1997 IEEE Design & Test of Computers  
Hardware circuits are often described using modeling or programming languages, and they are validated and implemented by executing software programs, which are sometimes conceived for the specific hardware  ...  Hardware/software co-design means meeting system-level objectives by exploiting the synergism of hardware and software through their concurrent design.  ...  Performance validation is often based on cosimulation of hardware and software [53] .  ... 
doi:10.1109/mdt.1997.573370 fatcat:e3chtb5h6ffpphp3ixtkspfm4y

Hardware-software codesign

P. Gupta
2002 IEEE potentials  
Hardware circuits are often described using modeling or programming languages, and they are validated and implemented by executing software programs, which are sometimes conceived for the specific hardware  ...  Hardware/software co-design means meeting system-level objectives by exploiting the synergism of hardware and software through their concurrent design.  ...  Performance validation is often based on cosimulation of hardware and software [53] .  ... 
doi:10.1109/45.983337 fatcat:qi4ochkozrfbrgml7azzlxro7e

Hardware/Software Codesign [chapter]

2008 System-on-Chip Design and Technologies  
Hardware circuits are often described using modeling or programming languages, and they are validated and implemented by executing software programs, which are sometimes conceived for the specific hardware  ...  Hardware/software co-design means meeting system-level objectives by exploiting the synergism of hardware and software through their concurrent design.  ...  Performance validation is often based on cosimulation of hardware and software [53] .  ... 
doi:10.1201/9781420051735.ch3 fatcat:vzpfaqbtozbonfdgewlalozmya

A case of system-level hardware/software co-design and co-verification of a commodity multi-processor system with custom hardware

Sungpack Hong, Tayo Oguntebi, Jared Casper, Nathan Bronson, Christos Kozyrakis, Kunle Olukotun
2012 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '12  
This paper presents an interesting system-level co-design and co-verification case study for a non-trivial design where multiple high-performing x86 processors and custom hardware were connected through  ...  In functional verification of such a system, we used a processor bus functional model (BFM) to combine native software execution with a cycle-accurate interconnect simulator and an HDL simulator.  ...  System-wide codesign and co-verification of hardware and software components [16] is especially essential for systems where multiple heterogeneous components are executing a single task in a tightly-coupled  ... 
doi:10.1145/2380445.2380524 dblp:conf/codes/HongOCBKO12 fatcat:4jgtca2j6nbyrhhb2na7q2li7m

Behaviour Driven Development for Hardware Design

Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Daniel Grosse, Rolf Drechsler
2018 IPSJ Transactions on System LSI Design Methodology  
Hardware verification requires a lot of effort. A recent study showed that on average, there are more verification engineers working on a project than design engineers.  ...  For software development the agile methodology as an incremental approach has been proposed and is heavily used.  ...  [21] propose four algorithms for computing small counterexamples that approximate the shortest case that are based on Dijkstra's algorithm for maximal strongly connected components [13] .  ... 
doi:10.2197/ipsjtsldm.11.29 fatcat:5yku64v3ljactlpjnup7jt26oa

Multigrid solvers in reconfigurable hardware

Safaa J. Kasbah, Issam W. Damaj, Ramzi A. Haraty
2008 Journal of Computational and Applied Mathematics  
The obtained results show better performance when compared to existing software versions.  ...  In this paper, we present a hardware implementation of the V-cycle Multigrid method for finding the solution of a 2D-Poisson equation.  ...  The obtained results have demonstrated that (1) MG algorithm outperforms the Jacobi and the SOR algorithms, on both hardware and software and (2) MG on hardware outperforms MG on GPP, where a speedup of  ... 
doi:10.1016/j.cam.2006.12.031 fatcat:izpjf3zfbbd6ho6zjjywqzerwm

Hardware/software co-design

Mike Mills, Greg Peterson
1998 ACM SIGAda Ada Letters  
Often architectural tradeoffs between hardware and software implementation must be performed early in the design cycle, resulting in potentially inefficient systems or subsystems.  ...  As technologies and costs in hardware and software implementation change over time, the best partitioning of system functionality into hardware and software components will also change.  ...  Several existing validation and verification techniques can be used to reduce the effort involved in maintaining Ada or VHDL.  ... 
doi:10.1145/301687.289528 fatcat:zos6ipqfv5cevfuifw44swhqsa

Hardware Certification for Safety-Critical Real-Time Systems

Andrew J. Kornecki, Janusz Zalewski
2009 IFAC Proceedings Volumes  
Some results of the authors' own study on tool qualification are presented.  ...  This paper discusses issues related to the RTCA document DO-254 Design Assurance Guidance for Airborne Electronic Hardware and its consequences for hardware certification.  ...  Findings contained herein are not necessarily those of the FAA.  ... 
doi:10.3182/20090210-3-cz-4002.00005 fatcat:xklmphvk25f43jcg2uvglcrsb4

Hardware/software co-design

Mike Mills, Greg Peterson
1998 Proceedings of the 1998 annual ACM SIGAda international conference on Ada - SIGAda '98  
Often architectural tradeoffs between hardware and software implementation must be performed early in the design cycle, resulting in potentially inefficient systems or subsystems.  ...  As technologies and costs in hardware and software implementation change over time, the best partitioning of system functionality into hardware and software components will also change.  ...  Several existing validation and verification techniques can be used to reduce the effort involved in maintaining Ada or VHDL.  ... 
doi:10.1145/289524.289528 dblp:conf/sigada/MillsP98 fatcat:k3wjjwxk5bcl3kcmggxirl2dym

Hardware/software co-design

G. De Michell, R.K. Gupta
1997 Proceedings of the IEEE  
Hardware circuits are often described using modeling or programming languages, and they are validated and implemented by executing software programs, which are sometimes conceived for the specific hardware  ...  Hardware/software co-design means meeting system-level objectives by exploiting the synergism of hardware and software through their concurrent design.  ...  Performance validation is often based on cosimulation of hardware and software [53] .  ... 
doi:10.1109/5.558708 fatcat:vyrbdbynszel3ku424iqlkh3sm

Dynamic Hardware Development

Stephen Craven, Peter Athanas
2008 International Journal of Reconfigurable Computing  
Benchmarking numbers are provided, which validate the productivity enhancements this approach provides.  ...  While the trend in digital design is towards higher levels of design abstractions, forgoing hardware description languages in some cases for high-level languages, the development of a reconfigurable design  ...  improvement increases to 49%, approximating the results for the coprocessor application.  ... 
doi:10.1155/2008/901328 fatcat:3itrrcxyhjaijh2fjkhtsap2jy

Consolidating Security Notions in Hardware Masking

Lauren De Meyer, Begül Bilgin, Oscar Reparaz
2019 Transactions on Cryptographic Hardware and Embedded Systems  
In this paper, we revisit the security conditions of masked hardware implementations.  ...  We also treat the notion of (strong) noninterference from an information-theoretic point-of-view in order to unify the different security concepts and pave the way to the verification of composability  ...  When the line is dotted, it is only valid for security order d = 1. The full lines are for any order d. Definition 1 ( 1 Simulatability [BBP + 16]).  ... 
doi:10.13154/tches.v2019.i3.119-147 dblp:journals/tches/MeyerBR19 fatcat:cn3vamlocrfjldkowuagmiwi2q
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