Filters








171 Hits in 8.4 sec

Random Adjacent Sequences [chapter]

René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2002 IFIP Advances in Information and Communication Technology  
By proving the effectiveness of universal test sequences produced by such a generation technique in detecting stuck-at, path delay and bridging faults, we demonstrate that using RSIC generation is one  ...  In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Input Change (RSIC) generation, that can be used to generate tests for many arbitrary misbehaviors  ...  Teixeira and his team from the Technical University of Lisboa (INESClIST) who provided us with the lists of realistic bridging faults experienced. 6.  ... 
doi:10.1007/978-0-387-35597-9_35 fatcat:wle5btbz7ndl3laixao5ptff7y

Sequential Circuit BIST Synthesis Using Spectrum and Noise from ATPG Patterns

Nitin Yogi, Vishwani D. Agrawal
2008 2008 17th Asian Test Symposium  
As an example, the FlexTest ATPG produced 55110 patterns for s38417, detecting 15472 of 31180 stuck-at faults.  ...  Sixty four-thousand of our BIST patterns detected 17020 faults as compared to 4244 detected by a previously reported spectral BIST method utilizing similar hardware overhead.  ...  FlexTest Hadamard BIST Circuit Fault Fault cov. (%) Fault cov. (%) BIST vectors cov. No. of at 64K at 128K for FlexTest (%) vectors vectors vectors ATPG cov.  ... 
doi:10.1109/ats.2008.64 dblp:conf/ats/YogiA08 fatcat:mg6vgcpx2jfyxfthqbgchqhu34

STARBIST

K. H. Tsai, S. Hellebrand, J. Rajski, M. Marek-Sadowska
1997 Proceedings of the 34th annual conference on Design automation conference - DAC '97  
This paper presents a new scan-based BIST scheme which achieves very high fault coverage without the deficiencies of previously proposed schemes.  ...  Experimental results demonstrate that a very high fault coverage can be obtained without any modification of the mission logic, no test data to store and very simple BIST hardware which does not depend  ...  Acknowledgment The authors are very grateful to Rob Thompson for the helps of ATPG in the experiments.  ... 
doi:10.1145/266021.266203 dblp:conf/dac/TsaiHRM97 fatcat:whptwcv32zff3aikdvvrgjf44a

Memory less Rotation Based BIST with Low Area Overhead

Drusya J U, S.Prabu Venkateswaran
2014 IOSR Journal of VLSI and Signal processing  
It can provide 100% fault coverage for all testable stuck-at faults.  ...  BIST is an efficient method for testing the circuits, area overhead is the main problem associated with BIST.  ...  The weighted random test (which means that the primary inputs are given individual probabilities (weights) of being 1) method [5] is presented to enhance the detectability of hard-todetect faults.  ... 
doi:10.9790/4200-04231217 fatcat:qs2mqp7dsjft5hfiv3qbmnebui

Bit Swapping and Cell Ordering on Finding Faults in Test Pattern Generation using BIST

Anandhi. K
2018 International Journal for Research in Applied Science and Engineering Technology  
Testing for delay and stuck-at faults requires two pattern tests and test sets are usually large. Built-in self-test (BIST) schemes are attractive for such comprehensive testing.  ...  During the pseudorandom testing phase, an LP weighted random test pattern generation scheme is used by disabling a part of scan chains.A novel low-power bit-swapping LFSR (BS-LFSR) is used to minimize  ...  The fault coverage of stuck at fault (modelled defects) by pseudo-random sequences is evaluated and analyzed.  ... 
doi:10.22214/ijraset.2018.5062 fatcat:apnd3jh4sbehbbiifgcdasally

Strategies and Techniques for Optimizing Power in BIST: A Review

Amandeep Singh, P. Mohan Kumar, Mohinder Bassi
2014 International Journal of Computer Applications  
Linear Feedback Shift Register (LFSR) in BIST generates pseudo-random patterns for detecting the faults, increasing the power consumption during testing, boosting the need to add power optimizations to  ...  Built in self test (BIST) and scan-based BIST are the techniques used for testing and detecting the faulty components in the VLSI circuit.  ...  The experimental results on ISCAS'85 Benchmark circuit and viterbi decoder for error detection and correction showed up 26% to 64% reduction in the number of WSAp without compromising on stuck-at fault  ... 
doi:10.5120/14976-3175 fatcat:pg7rprxbmngghg477zkegneh6e

Design and Development of a Modified AXI Based BIST Technique for Memory Architectures

2019 International journal of recent technology and engineering  
Different BIST modules need to be used to detect faults in different memories. As a result, design complexity increases.  ...  Built In Self Test (BIST) is a hardware memory test architecture deployed in many System on Chip devices to enable fault detection.  ...  The coverage of the proposed algorithm is high and the stuck at 0 and 1 faults are detected. In addition to this CLB faults, bridge faults, wire open and delay faults have been identified uniquely.  ... 
doi:10.35940/ijrte.d4446.118419 fatcat:77axnucgyjberony2vjxs5ajoq

BISD: Scan-based Built-In self-diagnosis

Melanie Elm, Hans-Joachim Wunderlich
2010 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)  
Built-In Self-Test (BIST) is less often applied to random logic than to embedded memories due to the following reasons: Firstly, for a satisfiable fault coverage it may be necessary to apply additional  ...  The paper at hand proposes a viable, effective and cost efficient solution for the second problem. The paper presents a new method for Built-In Self-Diagnosis (BISD).  ...  We would like to thank NXP for providing the circuits and Stefan Holst for hints on the implementation.  ... 
doi:10.1109/date.2010.5456997 dblp:conf/date/ElmW10 fatcat:44lr6533o5haha6l6ggbv5zli4

A Low Power BIST TPG for High Fault Coverage

R. Varatharajan, Lekha R.
2012 International Journal of Information Engineering and Electronic Business  
The proposed BIST comprised of three TPGs: Low transition random TPG (LT-RTPG), 3weight weighted random BIST (3-weight ERBIST) and Dual-speed LFSR (DS-LFSR).  ...  The 3-weight WRBIST is used to reduce the test sequence lengths by improving detection probabilities of random pattern resistant faults (RPRF).  ...  However, BIST using only pseudo random patterns doesn't provide high fault coverage due to the existence of random pattern resistant faults (RPRF).  ... 
doi:10.5815/ijieeb.2012.04.03 fatcat:2av6wpwhezdjzil32ogke6jlsy

Markov source based test length optimized SCAN-BIST architecture

Aftab Farooqi, Richard O. Gale, Sudhakar M. Reddy, Brian Nutter, Chris Monico
2009 2009 10th International Symposium on Quality of Electronic Design  
Design for Scan BIST √ √ √ √ √ √ √ Yu, Reddy, et.al, Weighted Pseudo-Random BIST for N-detection √ √ √ √ √ √ √ Yu, Reddy, et.al, Circuit Independent Weighted Pseudo-Random √ √ √ √  ...  coverage of the stuck-at faults in seven phases.  ... 
doi:10.1109/isqed.2009.4810380 dblp:conf/isqed/FarooqiGRNM09 fatcat:32fpk333jneidnhn7wonk4uaqi

A New Hybrid Test Pattern Generator for Stuck-at –Fault and Path Delay Fault in Scan Based Bist

C Karthikeyini, K Anandhi
2018 International Journal of Engineering & Technology  
Testing for delay and stuck-at faults needs a pattern of two checks and test sets square measure sometimes more. Built self-test (BIST) schemes square measure enticing for such comprehensive testing.  ...  The planned approach is predicated on weighted pseudorandom testing and uses a unique approach for pressing and storing the load sets.  ...  Combination of Test Pattern Generation for Delay Fault And Stuck-at-Fault Detection of these faults needs two-pattern tests.  ... 
doi:10.14419/ijet.v7i3.27.18000 fatcat:6yjqmilpzvannezzozhezugmdi

A seed selection procedure for LFSR-based random pattern generators

Kenichi Ichino, Ko-ichi Watanabe, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki
2003 Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC  
We propose a technique of selecting seeds for the LFSR-based test pattern generators that are used in VLSI BISTs.  ...  Our method can be used for both test-per-clock and test-per-scan BISTs. The procedure is based on vector representations over , where m is the number of LFSR stages.  ...  Weighted pseudo random testing puts test vectors into the CUT, where each bit of the vectors has weighted probabilities of "0" or "1", so that it can detect more faults than the original pattern [6] [  ... 
doi:10.1145/1119772.1119963 dblp:conf/aspdac/IchinoWAFI03 fatcat:uojy34ghlzfnpaegsx3bwhxig4

Designing asynchronous sequential circuits for random pattern testability

O.A. Petlin, S.B. Furber, A.M. Romankevich, V.V. Groll
1995 IEE Proceedings - Computers and digital Techniques  
The total number of random test patterns required to detect all the stuck-at faults in the data processing blocks and control blocks is determined by the total number of tests for the combinational logic  ...  A case study of a register destination decoder designed for random pattern testability is presented to demonstrate the practicability of the proposed design approach.  ...  The analysis of the circuit illustrated in Figure 4 shows that the number of random test patterns required to detect all the single stuck-at faults in it is equal to the number of test patterns for detecting  ... 
doi:10.1049/ip-cdt:19951982 fatcat:uaiisxtwzvdahfvbrtza3v3zb4

POWERTEST: a tool for energy conscious weighted random pattern testing

Xiaodong Zhang, K. Roy, S. Bhawmik
1999 Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)  
With that in mind we present an energy conscious weighted random pattern testing technique for Built-In-Self-Test BIST applications.  ...  We observed that a single input distribution or weights may not be su cient for some random-pattern resistant circuits, while multiple distributions consume larger area.  ...  For any i n ternal node A, if P t1 P A P t2 we s a y a n y stuck-at fault in node A is easily detectable and can be neglected in the cost function.  ... 
doi:10.1109/icvd.1999.745191 dblp:conf/vlsid/ZhangRB99 fatcat:2gc6wdr6bfcytjg2seeavi7ryu

Implementation and Utilization of LBIST for 16 bit ALU

2019 VOLUME-8 ISSUE-10, AUGUST 2019, REGULAR ISSUE  
This low power pattern generator consists of a pseudo random pattern generator (PSPR) which can be a linear feedback shift register or ring generator.  ...  In this methodology, controls for operation of generator are selected automatically. Selection of all the controls is made simple and accurate for the tuning.  ...  Using minimum test patterns with only small area overhead, this combinational logic block, intended for a particular COT, can be designed to accomplish nearly 100% single stuck-at fault coverage [1] .  ... 
doi:10.35940/ijitee.j9266.0881019 fatcat:liwg4qhquzamzmdycjv2jvjlpa
« Previous Showing results 1 — 15 out of 171 results