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HW/SW co-designed processors: Challenges, design choices and a simulation infrastructure for evaluation
2017
2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)
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HW/SW co-designed processors like Nvidia Denver, are emerging as a promising alternative. ...
This paper identifies the key challenges that HW/SW codesigned processors face and the basic requirements for a simulation infrastructure targeting these architectures. ...
building a simulation infrastructure for HW/SW co-designed processors. • Presents DARCO, a complete infrastructure for investigating HW/SW co-designed processors. • Characterizes the software layer of ...
doi:10.1109/ispass.2017.7975290
dblp:conf/ispass/KumarCBPSGMG17
fatcat:h7zmsyabebbhjitopdldmsfadm
A Co-designed HW/SW Approach to General Purpose Program Acceleration Using a Programmable Functional Unit
2011
2011 15th Workshop on Interaction between Compilers and Computer Architectures
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Results presented in this paper show that this HW/SW co-designed approach produces average speedups in performance of 17% in SPECFP and 10% in SPECINT, and up-to 33%, over modern out-of-order processor ...
In this paper, we propose a novel programmable functional unit (PFU) to accelerate general purpose application execution on a modern out-of-order x86 processor in a complexity-effective way. ...
Hence, we conclude that a new generation of out-of-order processors can be co-designed for higher performance in a complexity-effective way. ...
doi:10.1109/interact.2011.10
dblp:conf/IEEEinteract/DebCG11
fatcat:szdjyl73jrhx7pug2hsq7pge5u
Future Automotive HW/SW Platform Design (Dagstuhl Seminar 19502)
2020
Dagstuhl Reports
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This report documents the program and the outcomes of Dagstuhl Seminar 19502 "Future Automotive HW/SW Platform Design". ...
automotive HW/SW platforms, particularly focusing on predictability of systems regarding extra-functional properties, safe integration of hardware and software components and programmability and optimization ...
about uncertainty and the guarantees that can be provided either with machine learning or with other techniques, linking this to model order reduction to reduce the complexity of the models that are used for ...
doi:10.4230/dagrep.9.12.28
dblp:journals/dagstuhl-reports/ZiegenbeinSHS19
fatcat:gvrg2tj5enh3rnwtvquch54vo4
Effective Platform-Level Exploration for Heterogeneous Multicores Exploiting Simulation-Induced Slacks
2014
Proceedings of Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms - PARMA-DITAM '14
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In this paper, we propose (a) a platform design methodology that exploits simulation-induced slacks generated by avoiding simulation re-initializations and exploits the gained time for HLS, and (b) a DSE ...
tool-flow which takes into account multiple HW/SW partitioning schemes and intelligently schedules system evaluations. ...
framework, while additionally considering HW/SW co-design application par-titioning decisions. ...
doi:10.1145/2556863.2556864
dblp:conf/hipeac/Sotiriou-Xanthopoulos14
fatcat:pljw7z42h5c6jd45dfamhde7sq
Adaptive Cache Warming for Faster Simulations
2017
Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools - RAPIDO '17
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ACW takes advantage of the virtualization-based fast-forwarding to search for the minimum warming time required during simulation. ...
As a result, sampled simulations taking advantage of virtualization for fast-forwarding find their execution time dominated by functional warming. ...
ACKNOWLEDGMENTS This work was funded in part by the Swedish Science Council (grant 2014-5480), the Swedish Foundation for Strategic Research (grant FFL12-0051), the Uppsala Programming for Multicore Architectures ...
doi:10.1145/3023973.3023974
fatcat:t63xhqrxz5c3ndku7nvmd2gr7a
SoftHV
2011
Proceedings of the 8th ACM International Conference on Computing Frontiers - CF '11
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In this paper we propose SoftHV, a high-performance HW/SW co-designed in-order processor that performs horizontal and vertical fusion of instructions. ...
Overall, we show that such a co-designed processor based on an in-order core provides a compelling alternative to out-of-order processors for the low-end domain where high-performance at a low-complexity ...
PERFORMANCE EVALUATION
Experiment Methodology Our proposed HW/SW co-designed processor is modeled using PTLSim [24] . We have implemented an in-order processor core along with a Cd-VM. ...
doi:10.1145/2016604.2016606
dblp:conf/cf/DebCG11
fatcat:bdbwx32qjjcyvizvsxlq3dcj4a
PowerChop
2016
SIGARCH Computer Architecture News
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This work introduces POWERCHOP, a novel technique that leverages the unique capabilities of HW/SW co-designed hybrid processors to enact unit-level power management at the application phase level. ...
processor by 19% (up to 40%) while introducing just 2% slowdown. ...
ACKNOWLEDGEMENTS We would like to thank our anonymous reviewers for their comments. This work was sponsored by National Science Foundation grants CCF-1302682 and CCF-1553485. ...
doi:10.1145/3007787.3001152
fatcat:wwskj4vowvhxti5zsulreyful4
PowerChop: Identifying and Managing Non-critical Units in Hybrid Processor Architectures
2016
2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA)
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This work introduces POWERCHOP, a novel technique that leverages the unique capabilities of HW/SW co-designed hybrid processors to enact unit-level power management at the application phase level. ...
processor by 19% (up to 40%) while introducing just 2% slowdown. ...
ACKNOWLEDGEMENTS We would like to thank our anonymous reviewers for their comments. This work was sponsored by National Science Foundation grants CCF-1302682 and CCF-1553485. ...
doi:10.1109/isca.2016.22
dblp:conf/isca/LaurenzanoZCTM16
fatcat:bzbr4nle4ngzthlm57gtxgn6oy
Technology Validation: NMP ST8 Dependable Multiprocessor Project II
2007
2007 IEEE Aerospace Conference
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(COTS) processors for on-board computing has become a critical need. ...
With the ever-increasing demand for higher bandwidth and processing capacity of today's space exploration, space science, and defense missions, the ability to efficiently apply Commercial-Off-The-Shelf ...
Testing
Technology in
Relevant Environment
Technology in Relevant
Environment for Full Flight Design
Flight
Preliminary Experiment
HW & SW
Design & Analysis
Final Experiment
HW & SW
Design ...
doi:10.1109/aero.2007.352784
fatcat:q27bk5esn5gvlnppr47aeuaowm
iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches
2014
2014 IEEE 32nd International Conference on Computer Design (ICCD)
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Negative bias temperature instability (NBTI) is a major cause of concern for chip designers because of its inherent ability to drastically reduce silicon reliability over the lifetime of the processor. ...
A unique feature of iRMW is its intelligent use of low-leakage & NBTI-tolerant embedded-DRAM cells as an alternative to SRAM-cells for storing important state information. ...
Simulation Setup 1) Architecture-level simulations: Our architecture-level analysis is performed using DARCO simulation infrastructure that is targeted more towards evaluating HW/SW co-designed virtual ...
doi:10.1109/iccd.2014.6974664
dblp:conf/iccd/GanapathyCGR14
fatcat:5aoa5a5hdnfpzpyb2svxqjvcbm
Enabling Efficient Alias Speculation
2015
Proceedings of the 16th ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems 2015 CD-ROM - LCTES'15
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Microprocessors designed using HW/SW codesign principles, such as Transmeta TM Efficeon TM and the soon-to-ship NVIDIA 64-bit Tegra R K1, use dynamic binary optimization to extract instruction-level parallelism ...
By using a more compact encoding for memory access ranges for memory instructions, alias coalescing simultaneously reduces the alias register pressure in SMARQ by a geomean of 26.09% and 39.96%, and the ...
Acknowledgements We would like to thank the many outstanding engineers at Intel Labs for their comments on this work. We thank the anonymous reviewers for their insightful comments. ...
doi:10.1145/2670529.2754964
dblp:conf/lctrts/GhoshPR15
fatcat:65wpuupyvffl3des4rng4xs5ii
PPT-Multicore: Performance Prediction of OpenMP applications using Reuse Profiles and Analytical Modeling
[article]
2021
arXiv
pre-print
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We present PPT-Multicore, an analytical model embedded in the Performance Prediction Toolkit (PPT) to predict parallel application performance running on a multicore processor. ...
This paper has been approved for unlimited public distribution under LA-UR-21-22749. ...
David Newsom for donating several machines to the PEARL laboratory at NMSU. Some of the experiments in this paper were run on the donated machines. ...
arXiv:2104.05102v1
fatcat:mtcyzxf5g5hslogtp5mra5z7wa
Prosiding Penyelidikan Prasiswazah, Issue No. 1, 2021
2021
Zenodo
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In addition, the HW/SW system runs in Zynq-7000 SoC
hardware with AXI DMA and ARM processor. ...
For face recognition application used in this study.
the HW/SW implementation, an embedded Before the embedded software implemented into
HW/SW system design is required ...
doi:10.5281/zenodo.5771436
fatcat:gwlbmjtgrjae7jbtjwuksnavoi
Prosiding Penyelidikan Prasiswazah, Issue No. 1, 2021
2021
Zenodo
Preserved Fulltext
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The file type is application/pdf.
In addition, the HW/SW system runs in Zynq-7000 SoC
hardware with AXI DMA and ARM processor. ...
For face recognition application used in this study.
the HW/SW implementation, an embedded Before the embedded software implemented into
HW/SW system design is required ...
doi:10.5281/zenodo.5771476
fatcat:r74w7ktrnbeglcsquirfsfw4p4
Prosiding Penyelidikan Prasiswazah, Issue No. 1, 2021
2021
Zenodo
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2021; you can also visit the original URL.
The file type is application/pdf.
In addition, the HW/SW system runs in Zynq-7000 SoC
hardware with AXI DMA and ARM processor. ...
For face recognition application used in this study.
the HW/SW implementation, an embedded Before the embedded software implemented into
HW/SW system design is required ...
doi:10.5281/zenodo.5771566
fatcat:lgrttq6krzhwtp54qdmqqxueoy
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