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Wafer-Scale Integration of Systolic Arrays
1985
IEEE transactions on computers
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Abstract: VLSI technologists are fast developing wfafer-scale integration. ...
-Key Words'channel width, fault-tolerant systems, probabilistic analysis, spannin tree, Bystolic arrays, travelling salesman problem, tree of meshes, VLSI, wafer-scale integration, wire Thi neearch was ...
Special thanks in particular to Jef" Siskind and Jay Southard of Lincoln Lab for exploring the practical aspects of our algorithms with us. ...
doi:10.1109/tc.1985.1676584
fatcat:d7nrl5ubqbgkhepwnkejicdaxu
Neuromorphic microelectronics from devices to hardware systems and applications
2016
Nonlinear Theory and Its Applications IEICE
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A regain of interest has been observed in the middle of the 2010s', which manifests itself from the emergence of large-scale projects integrating various computational and hardware perspectives, by the ...
increased interest and involvement of industry and the growth of the volume of scientific publications. ...
SIMD arrays (central control) and systolic arrays (local control) in the form of linear systolic arrays, also referred to as ring systolic arrays or two-dimensional systolic arrays, have been applied as ...
doi:10.1587/nolta.7.468
fatcat:2lvkjxhetnghtmbbow4mfcqqjm
Loop-based design and reconfiguration of wafer-scale linear arrays with high harvest rates
1991
IEEE Journal of Solid-State Circuits
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The designs are appropriate for implementing linear arrays of wafer-scale memory and processor architectures. ...
Application of boundary scan to parallel testing and on-wafer diagnosis of the arrays is described. W. Kent Fuchs (S'80-M'85-SM'90) received the B. ...
ACKNOWLEDGMENT The authors wish to acknowledge the discussions and contributions of R. Horst, J. Patel, and W. Shi in the development of this paper. ...
doi:10.1109/4.78242
fatcat:i6n6xzi57jaargxgxzcgogwu2y
Computer architecture for digital signal processing
1985
Proceedings of the IEEE
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Such architectures are seen as the result of constraining influences from the nature of digital signal processing algorithms, architectural technfques includ ing appropriate choice of primitive elements ...
In this paper, a comprehensive overview of Computer Architecture for Digital Signal Processing is given. ...
In another example, a systolic design for dynamic timewarping has been specified for wafer scale design [35] . ...
doi:10.1109/proc.1985.13218
fatcat:bzr4iop4bngdfkm57mzm52nnry
High-speed signal processing using systolic arrays over finite rings
1988
IEEE Journal on Selected Areas in Communications
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Linear systolic arrays, formed with multiple elements, each of a single generic form, are used for all calculations. ...
Examples of DSP applications are given to illustrate the technique, and sample cell and array VLSI layouts are presented for a 3µ CMOS process. ...
Raja for the design of the VLSI cells and FIR filter layouts. ...
doi:10.1109/49.1918
fatcat:ck3zdduv5javhgok33yyub6sze
3D heterogeneous sensor system on a chip for defense and security applications
2004
Unattended/Unmanned Ground, Ocean, and Air Sensor Technologies and Applications VI
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A specific scenario is discussed in detail wherein a set of four types of sensors, namely an array of acoustic and seismic sensors, an active pixel sensor array, and an uncooled IR imaging array are placed ...
This paper describes a new concept for ultra-small, ultra-compact, unattended multi-phenomenological sensor systems for rapid deployment, with integrated classification-and-decision-information extraction ...
approach to extending performance beyond device and interconnect scaling limits [1] - [14] . 3-D integration provides high device integration density, high interconnectivity, reduction of long global ...
doi:10.1117/12.548199
fatcat:fyftqqciqbckfen4zxvniyjila
Primer on silicon neuromorphic photonic processors: architecture and compiler
2020
Nanophotonics
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Neuromorphic photonics aims to map physical models of optoelectronic systems to abstract models of neural networks. ...
A silicon photonic integration industry promises to bring manufacturing ecosystems normally reserved for microelectronics to photonics. ...
In CMOS, MVM operations are typically instantiated using systolic arrays [140] or SIMD units [141] , although there are some other architectures that use aspects of both [142] . ...
doi:10.1515/nanoph-2020-0172
fatcat:m45ztrraojalxbygq33tat7fjq
A Customized Many-Core Hardware Acceleration Platform for Short Read Mapping Problems Using Distributed Memory Interface with 3D–Stacked Architecture
2016
Journal of Signal Processing Systems
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Assembling of those short reads poses a challenge on the mapping of reads to a reference genome in terms of both sensitivity and execution time. ...
Rapidly developing Next Generation Sequencing technologies produce huge amounts of short reads that consisting randomly fragmented DNA base pair strings. ...
frequency of systolic array. ...
doi:10.1007/s11265-016-1204-8
fatcat:fmfr633cdjc3tmfkoksgwmk6za
field-programmable gate array
[chapter]
2000
Computer Science and Communications Dictionary
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This reduction in work comes from two optimizations: one, since the base wafer of gate arrays is predetermined, personalizing it for different integrated circuits requires manufacturers to generate only ...
Not only does reusing a single wafer enable manufacturers to mass-produce those wafers for high availability while maintaining low amortized cost per wafer, it also allows the standardization of bonding ...
doi:10.1007/1-4020-0613-6_7086
fatcat:wms2fgic45bwtcjrhr35mzcl64
Micropillar Arrays for High Sensitivity Sensors
2014
Materials Research Society Symposium Proceedings
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Arrays of pillars of radii between 1 and 100 microns and lengths of 5 to 100 microns have been reported [28] over cm scale areas of the silicon wafer. ...
Time scale characteristics of sensor response The time scale characteristics of the micropillar array was measured using a digital converter (EVAL-AD7746EBZ, Analog Devices) circuit. ...
doi:10.1557/opl.2014.788
fatcat:w74ufs44nne2dhyhptvltvtqbi
Fault-tolerant computing: fundamental concepts
1990
Computer
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System-level fault tolerance requires considerable work, especially in wafer-scale systems and other highly integrated systems. which are subject to multiple component failures. ...
Large systolic arrays, massively parallel architectures, and other large-scale distributed systems with complex interconnection networks present challenges in system control, performance, and fault tolerance ...
doi:10.1109/2.56849
fatcat:67z4gv7pxvg57px75gkmrf7oba
Artificial neural networks in hardware: A survey of two decades of progress
2010
Neurocomputing
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Parallel digital implementations employing bit-slice, systolic, and SIMD architectures, implementations for associative neural memories, and RAM based implementations are also outlined. ...
HNN research has witnessed a steady progress for more than last two decades, though commercial adoption of the technology has been relatively slower. ...
Multi-Chip Modules or Wafer-Scale Integration hold further promise for implementing such large networks. ...
doi:10.1016/j.neucom.2010.03.021
fatcat:regzu6sshvekzd5wxcuaiytgqu
Programmable active memories in real-time tasks: implementing data-driven triggers for LHC experiments
1995
Nuclear Instruments and Methods in Physics Research Section A : Accelerators, Spectrometers, Detectors and Associated Equipment
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The algorithms were implemented for a decision frequency of 100 kHz, on different data-driven programmable devices based on structures of field-programmable gate arrays and memories. ...
The implementations were demonstrated at full speed with emulated input, and were also integrated into a prototype detector running in a test beam at CERN, in June 1994. ...
This type of low-level description is made convenient by the use of basic programming concepts such as arrays, loops, procedures and data abstraction. ...
doi:10.1016/0168-9002(94)01397-7
fatcat:zhxa6dj4jvacdd5zbzj3nnvaim
Computer vision algorithms on reconfigurable logic arrays
1999
IEEE Transactions on Parallel and Distributed Systems
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Computer Vision Algorithms on Reconfigurable Logic Arrays By Nalini K. ...
With recent advances in very large scale integration (VLSI) technology, an application speci c integrated circuit (ASIC) can provide the best performance in terms of total execution time. ...
Ramacher 176] describes the architecture of SYNAPSE { a systolic neural signal processor using a 2-D array of systolic elements. ...
doi:10.1109/71.744833
fatcat:htpcqypklnghvfdedyl7dneyhu
Synchronizing Large VLSI Processor Arrays
1985
IEEE transactions on computers
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This result cannot be extended to twodimensional arrays, however; the paper shows that under this assumption, it is impossible to run a clock such that the maximum clock skew between two communicating ...
In this case, it is shown that even assuming that physical variations along clock lines can produce skews between wires of the same length, any one-dimensional processor array can be correctly synchronized ...
As a result, the clocked array may be extended to contain any number of cells using the same clocked cell design. ...
doi:10.1109/tc.1985.1676619
fatcat:hiwkzsvkibhmzj2g7kixe5gsja
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