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WCET analysis for multi-core processors with shared buses and event-driven bus arbitration

Michael Jacobs, Sebastian Hahn, Sebastian Hack
2015 Proceedings of the 23rd International Conference on Real Time and Networks Systems - RTNS '15  
Data cache Round-robin bus arbitration Setup for experiments: Michael Jacobs WCET Analysis for Multi-Core Processors November 5, 2015 14 / 19 computer science saarland university Iteration  ...  Results normalized to analysis ignoring bus interference Geometric mean over normalized results Michael Jacobs WCET Analysis for Multi-Core Processors November 5, 2015 7 / 19 computer science  ... 
doi:10.1145/2834848.2834872 dblp:conf/rtns/JacobsHH15 fatcat:pys6awt2qzgerat73csvia27aq

Impact of Resource Sharing on Performance and Performance Prediction: A Survey [chapter]

Andreas Abel, Florian Benz, Johannes Doerfert, Barbara Dörr, Sebastian Hahn, Florian Haupenthal, Michael Jacobs, Amir H. Moin, Jan Reineke, Bernhard Schommer, Reinhard Wilhelm
2013 Lecture Notes in Computer Science  
Multi-core processors are increasingly considered as execution platforms for embedded systems because of their good performance/energy ratio.  ...  In this paper, we survey recent work on the impact of shared buses, caches, and other resources on performance and performance prediction.  ...  For that reason, currently, no sound timing-analysis method for multi-core platforms with shared resources exists.  ... 
doi:10.1007/978-3-642-40184-8_3 fatcat:vltmy7q5xbdthgtszl3gxn2x3q

Data Bus Slicing for Contention-Free Multicore Real-Time Memory Systems

Javier Jalle, Eduardo Quinones, Jaume Abella, Luca Fossati, Marco Zulianello, Francisco J. Cazorla
2016 2016 11th IEEE Symposium on Industrial Embedded Systems (SIES)  
Existing techniques to control memory contention based on time-sharing memory access do not scale well with increasing complexity of multicores, leading to a rapid increase of WCET estimates.  ...  Our evaluation on a solid space case-study shows that the proposed memory organization provides contention-free memory access facilitating timing analysis and tightening WCET estimates. © 2016 IEEE.  ...  The research leading to these results has received funding from the European Space Agency under contract NPI 4000102880 and the Ministry of Science and Technology of Spain under contract TIN-2015-65316  ... 
doi:10.1109/sies.2016.7509441 dblp:conf/sies/JalleQAFZC16 fatcat:qgr2ugdfr5fj7gqdqe4kpk4okm

A Framework for the Derivation of WCET Analyses for Multi-core Processors

Michael Jacobs, Sebastian Hahn, Sebastian Hack
2016 2016 28th Euromicro Conference on Real-Time Systems (ECRTS)  
This makes a precise worst-case execution time (WCET) analysis for multi-core processors challenging.  ...  Multi-core processors share common hardware resources between several processor cores.  ...  ACKNOWLEDGMENTS The authors would like to thank Mihail Asavoae, Florian Haupenthal, Max John, Jan Reineke, and Reinhard Wilhelm for many comments and interesting discussions.  ... 
doi:10.1109/ecrts.2016.19 dblp:conf/ecrts/00020H16 fatcat:nanrhcgepfe27edssh26qztbge

Adapting TDMA arbitration for measurement-based probabilistic timing analysis

Miloš Panić, Jaume Abella, Eduardo Quiñones, Carles Hernandez, Theo Ungerer, Francisco J. Cazorla
2017 Microprocessors and microsystems  
We show how the execution time measurements taken as input for MBPTA need to be padded to obtain reliable and tight WCET estimates on top of TDMA-arbitrated hardware resources with no further hardware  ...  Bounds to WCET can be derived with deterministic timing analysis (DTA) and probabilistic timing analysis (PTA), each of which relies upon certain predictability properties coming from the hardware/software  ...  This work has also been partially supported by the Spanish Ministry of Economy and Competitiveness (MINECO) under grant TIN2015-65316-P and the HiPEAC Network of Excellence.  ... 
doi:10.1016/j.micpro.2017.06.006 fatcat:b5ziwe4lw5a73mqoufsqfiuogy

A generic and compositional framework for multicore response time analysis

Sebastian Altmeyer, Robert I. Davis, Leandro Indrusiak, Claire Maiza, Vincent Nelis, Jan Reineke
2015 Proceedings of the 23rd International Conference on Real Time and Networks Systems - RTNS '15  
Processor-Priority, and TDMA, and account for DRAM refreshes.  ...  We instantiate the framework for single level local data and instruction memories (cache or scratchpads), for a variety of memory bus arbitration policies, including: Round-Robin, FIFO, Fixed-Priority,  ...  Science and Technology) and co-financed by ERDF (European Regional Development This collaboration was partly due to the Dagstuhl Seminar on Mixed Criticality http://www.dagstuhl.de/15121.  ... 
doi:10.1145/2834848.2834862 dblp:conf/rtns/AltmeyerDIMNR15 fatcat:4ad3vtbawjer7otj44q4dbotqe

Hardware support for WCET analysis of hard real-time multicore systems

Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Guillem Bernat, Mateo Valero
2009 SIGARCH Computer Architecture News  
In this paper we propose a multicore architecture with shared resources that allows the execution of applications with hard real-time and non hard real-time constraints at the same time, providing time  ...  However, hard real-time embedded systems require time analyzability and current multicore processors are less analyzable than single-core processors due to the interferences between different tasks when  ...  We evaluate our proposal using a real WCET analysis tool and a real hard real-time application. In particular we evaluate a 4-core architecture with a shared L2 cache connected by a shared bus.  ... 
doi:10.1145/1555815.1555764 fatcat:m7rjwil5angjnhaltopzlnlszi

Hardware support for WCET analysis of hard real-time multicore systems

Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Guillem Bernat, Mateo Valero
2009 Proceedings of the 36th annual international symposium on Computer architecture - ISCA '09  
In this paper we propose a multicore architecture with shared resources that allows the execution of applications with hard real-time and non hard real-time constraints at the same time, providing time  ...  However, hard real-time embedded systems require time analyzability and current multicore processors are less analyzable than single-core processors due to the interferences between different tasks when  ...  We evaluate our proposal using a real WCET analysis tool and a real hard real-time application. In particular we evaluate a 4-core architecture with a shared L2 cache connected by a shared bus.  ... 
doi:10.1145/1555754.1555764 dblp:conf/isca/PaolieriQCBV09 fatcat:jm6din3libcjvkhqoiiwtnd5mq

An extensible framework for multicore response time analysis

Robert I. Davis, Sebastian Altmeyer, Leandro S. Indrusiak, Claire Maiza, Vincent Nelis, Jan Reineke
2017 Real-time systems  
An extensible framework for multicore response time analysis Davis, R.I.; Altmeyer, S.J.; Indrusiak, L.S.; Maiza, C.; Nelis, V.; Reineke, J.  ...  Acknowledgements This work was supported in part by the COST Action IC1202 TACLe, by the NWO Veni Project 'The time is now: Timing Verification for Safety-Critical Multi-Cores' by the Deutsche Forschungsgemeinschaft  ...  as part of the project PEP, by National Funds through FCT/MEC (Portuguese Foundation for Science and Technology) and co-financed by ERDF (European Regional Development  ... 
doi:10.1007/s11241-017-9285-4 fatcat:dg6qbbdzfnajxlbsje57ku2ryi

Identifying the sources of unpredictability in COTS-based multicore systems

Dakshina Dasari, Benny Akesson, Vincent Nelis, Muhammad Ali Awan, Stefan M. Petters
2013 2013 8th IEEE International Symposium on Industrial Embedded Systems (SIES)  
leading totemporal unpredictability, which mainly involve shared hardwareresources, such as buses, caches, and memories.  ...  We explore someof the existing work in timing analysis with respect to thesefeatures, identify their limitations, and present some unaddressedissues that must be dealt with to ensure safe deployment of  ...  The second factor is largely dependent on the bus arbitration mechanism. If the bus is TDMA driven, an idle slot is guaranteed to each requester (e.g. a core) at fixed predictable time instants.  ... 
doi:10.1109/sies.2013.6601469 dblp:conf/sies/DasariANAP13 fatcat:dg5rkpigebce7fkmpmbzry3fhm

Towards limiting the impact of timing anomalies in complex real-time processors

Pedro Benedicte, Jaume Abella, Carles Hernandez, Enrico Mezzetti, Francisco J. Cazorla
2019 Proceedings of the 24th Asia and South Pacific Design Automation Conference on - ASPDAC '19  
For the first time, we study the concept and impact of timing anomalies in measurement-based timing analysis, the most used in industry, showing that they require to be considered and handled differently  ...  Timing anomalies, deeply analyzed in static timing analysis, require specific solutions to bound their impact.  ...  With this policy, we guarantee that, in a 4-core processor, each core will be able to access the shared L2 cache 1 out of every 4 time slots.  ... 
doi:10.1145/3287624.3287655 dblp:conf/aspdac/BenedicteAHMC19 fatcat:fm2fhgmixfb2daa7ihonxa7mla

A Dual-Criticality Memory Controller (DCmc): Proposal and Evaluation of a Space Case Study

Javier Jalle, Eduardo Quinones, Jaume Abella, Luca Fossati, Marco Zulianello, Francisco J. Cazorla
2014 2014 IEEE Real-Time Systems Symposium  
Our evaluation with a multicore cycle-accurate simulator and a real space case study shows that DCmc enables deriving tight WCET estimates, regardless of the co-running payload applications, hence effectively  ...  In order to control the interaction (contention) among payload and control applications in the access to the main memory, reaching the goals of highbandwidth for the former and guaranteed timing bounds  ...  ACKNOWLEDGEMENTS The research leading to these results has received funding from the European Space Agency under NPI Contract 40001102880 and the FP7 grant agreement no. 287519 (parMERASA).  ... 
doi:10.1109/rtss.2014.23 dblp:conf/rtss/JalleQAFZC14 fatcat:22medwklovd5thgkqyntcy25lq

Adaptive TDMA bus allocation and elastic scheduling: A unified approach for enhancing robustness in multi-core RT systems

Paolo Burgio, Martino Ruggiero, Francesco Esposito, Mauro Marinoni, Giorgio Buttazzo, Luca Benini
2010 2010 IEEE International Conference on Computer Design  
This reduces the benefits given by the TDMA bus, which relies on the high level task analysis for a robust and efficient slot allocation.  ...  Next-generation real-time systems will be increasingly based on heterogeneous MPSoC design paradigms, where predictability and performance will be key issues to deal with.  ...  Each row is composed by the WCETs of all tasks working with the selected bus bandwidth assignment. The WCET values can be obtained using a static code profiler and analysis tool such as [19] .  ... 
doi:10.1109/iccd.2010.5647792 dblp:conf/iccd/BurgioREMBB10 fatcat:gghtq5cldvfezgirmj5yjal5l4

Cache-conscious off-line real-time scheduling for multi-core platforms: algorithms and implementation

Viet Anh Nguyen, Damien Hardy, Isabelle Puaut
2019 Real-time systems  
In this paper, we propose two scheduling techniques for multi-core architectures equipped with local instruction and data caches.  ...  Most schedulability analysis techniques for multi-core architectures assume a single Worst-Case Execution Time (WCET) per task, which is valid in all execution conditions.  ...  Acknowledgements The authors would like to thank Byron Hawkins and anonymous reviewers for their useful comments on this paper.  ... 
doi:10.1007/s11241-019-09333-z fatcat:e5sy2lcet5evtalbsmem6fmkca

Computing Safe Contention Bounds for Multicore Resources with Round-Robin and FIFO Arbitration

Gabriel Fernandez, Javier Jalle, Jaume Abella, Eduardo Quinones, Tullio Vardanega, Francisco J. Cazorla
2017 IEEE transactions on computers  
Most of those studies seek to derive a tight and sound upper-bound for the worst-case delay with which a processor resource may serve an incoming request, when its access is arbitrated using time-predictable  ...  Unfortunately however, that is rarely granted for commercial-of-the-shelf (COTS) processors.  ...  The authors would like to thanks Paul Caheny for his help with the proofreading of this document.  ... 
doi:10.1109/tc.2016.2616307 fatcat:brz2wqgujzaj3jg6p53umt3tdy
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