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Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors

Qiang Wu, Philo Juang, M. Martonosi, D.W. Clark
11th International Symposium on High-Performance Computer Architecture  
In this paper, we present a new intra-task online DVFS scheme for multiple clock domain (MCD) processors.  ...  In this work, we propose an alternative online DVFS scheme in which the reaction time is self-tuned and adaptive to application and workload changes.  ...  This work has been supported by NSF grants CCR-0086031 (ITR) and CNS-0410937. In addition, Martonosi's work is supported in part by Intel, IBM, and SRC.  ... 
doi:10.1109/hpca.2005.43 dblp:conf/hpca/WuJMC05 fatcat:lyomysbg6zczffcxvdcm5tt5mu

A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC–DC Converters in 28 nm FDSOI

2016 IEEE Journal of Solid-State Circuits  
This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC-DC (SC DC-DC) converters and adaptive clocking that generates  ...  Index Terms-Adaptive clock, DC-DC conversion, dynamic voltage and frequency scaling (DVFS), fully integrated converter, integrated voltage regulator, noninterleaved, RISC-V, simultaneous-switching, switched-capacitor  ...  Thomas, and A. Vladimirescu for their contributions.  ... 
doi:10.1109/jssc.2016.2519386 fatcat:f73wioqzmvfldi24e4sjujbxhi

System level analysis of fast, per-core DVFS using on-chip switching regulators

Wonyoung Kim, Meeta S. Gupta, Gu-Yeon Wei, David Brooks
2008 High-Performance Computer Architecture  
Dynamic voltage and frequency scaling (DVFS) is a well-known technique to reduce energy in digital systems, but the effectiveness of DVFS is hampered by slow voltage transitions that occur on the order  ...  In this paper, we describe and model these costs, and perform a comprehensive analysis of a CMP system with on-chip integrated regulators.  ...  The findings expressed in this material are those of the authors and do not necessarily reflect the views of the funding agencies.  ... 
doi:10.1109/hpca.2008.4658633 dblp:conf/hpca/KimGWB08 fatcat:r3osegzwubdfvclqjrzfrafwqy

Power reduction techniques for microprocessor systems

Vasanth Venkatachalam, Michael Franz
2005 ACM Computing Surveys  
We survey the "state of the art" in techniques that reduce the total power consumed by a microprocessor system over time.  ...  We conclude that power management is a multifaceted discipline that is continually expanding with new techniques being developed at every level.  ...  Dynamic Voltage Scaling In Multiple Clock Domain Architectures. A Globally Asynchronous, Locally Synchronous (GALS) chip is split into multiple domains, each of which has its own local clock.  ... 
doi:10.1145/1108956.1108957 fatcat:3v56rcg7yrejffkqp64hev4exi

Integrated CPU and l2 cache voltage scaling using machine learning

Nevine AbouGhazaleh, Alexandre Ferreira, Cosmin Rusu, Ruibin Xu, Frank Liberato, Bruce Childers, Daniel Mosse, Rami Melhem
2007 SIGPLAN notices  
New chip design with Multiple Clock Domains (MCD) opens the opportunity for fine-grain power management within the processor chip.  ...  When used with dynamic voltage scaling (DVS), we can control the voltage and power of each domain independently.  ...  The derived policy dynamically adapts the domains' voltages and frequencies to current workload in an MCD processor.  ... 
doi:10.1145/1273444.1254773 fatcat:bikzh3o5n5dhvggebybnq3zy4i

Optically-Clocked Instruction Set Extensions for High Efficiency Embedded Processors

Claudio Favi, Theo Kluter, Christian Mester, Edoardo Charbon
2012 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
We propose a technique to localize computation in Instruction Set Extensions (ISEs) that are clocked at very high speed with respect to the processor.  ...  frequency clock over long distances is avoided.  ...  ACKNOWLEDGMENT The authors would like to thank Zhong Zhong Ni at EPFL and Mohammad Karami and Mauro Scandiuzzo at TUDelft for their invaluable help during the design process.  ... 
doi:10.1109/tcsi.2011.2169730 fatcat:ysas6b6nijebtfxp55pgclvzam

A Hypervisor Architecture For Low-Power Real-Time Embedded Systems

Tomaso Poggi, Peio Onaindia, Mikel Azkarate-Askatsua, Kim Grüttner, Maher Fakih, Salavador Peiró, Patricia Balbastre
2018 Zenodo  
This paper presents a hypervisor architecture tailored to low-power real-time applications.  ...  Measurement results show that the extended hypervisor can obtain information on the power consumption and reduce it.  ...  ACKNOWLEDGEMENTS The research leading to these results has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 687902 (SAFEPOWER).  ... 
doi:10.5281/zenodo.1304095 fatcat:wamljvxm5zgy5a3y64konphzqm

Towards Energy-Aware Multi-Core Scheduling

J. Richling, J. H. Schönherr, G. Mühl, M. Werner
2009 PIK - Praxis der Informationsverarbeitung und Kommunikation  
cores in time.  ...  cores per processor and (ii) the increasing importance of energy-awareness in computing due to rising energy costs and environmental awareness.  ...  from mobile systems, namely the ability to dynamically adapt the clock frequency and voltage of a processor to the computing demand and to disable certain units of the processor when they are temporarily  ... 
doi:10.1515/piko.2009.0017 fatcat:pfwgq4fiw5ezhiovkf7fcjtkdq

Nanoelectronics: challenges and opportunities

Giovanni de Micheli
2007 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)  
execution times comply with application requirements and, in fact, are even 10% better on the SUNFLOOR topology. it all together … • ULP demands low-voltage operation • High throughput requires parallel  ...  Dynamic voltage scaling in processors • Razor [Austin -U Michigan] -Dynamic latency adjustment for NoCs • Terror [Tamhankar -Stanford] • Autonomic computing -Systems that understand and react  ...  built-in fault tolerance and predictable delays -On chip networks to provide units with structured communication -3-dimensional packages to support integration of different technologies • Novel design  ... 
doi:10.1109/vdat.2007.373195 fatcat:k4vwrb26c5a7rjfscrmm6ykrae

Nanoelectronics: Challenges and Opportunities [chapter]

Giovanni De Micheli
2006 Lecture Notes in Computer Science  
execution times comply with application requirements and, in fact, are even 10% better on the SUNFLOOR topology. it all together … • ULP demands low-voltage operation • High throughput requires parallel  ...  Dynamic voltage scaling in processors • Razor [Austin -U Michigan] -Dynamic latency adjustment for NoCs • Terror [Tamhankar -Stanford] • Autonomic computing -Systems that understand and react  ...  built-in fault tolerance and predictable delays -On chip networks to provide units with structured communication -3-dimensional packages to support integration of different technologies • Novel design  ... 
doi:10.1007/11847083_64 fatcat:tj4u5fm3jbazplfvxy5dtatndy

Variability Mitigation in Nanometer CMOS Integrated Systems: A Survey of Techniques From Circuits to Software

Abbas Rahimi, Luca Benini, Rajesh K. Gupta
2016 Proceedings of the IEEE  
| Variation in performance and power across manufactured parts and their operating conditions is an accepted reality in modern microelectronic manufacturing processes with geometries in nanometer scales  ...  First, we provide a review of key concepts with particular emphasis on timing errors caused by various variability sources.  ...  For instance, an on-die adaptive frequency controller changes clock frequency in response to error rate reported by transition detector circuits [43] .  ... 
doi:10.1109/jproc.2016.2518864 fatcat:sxrsu3excbdg5p7sk4iczz262y

Design and Run-time Reliability at the Electronic System Level

Björn Sander, Andreas Bernauer, Wolfgang Rosenstiel
2010 IPSJ Transactions on System LSI Design Methodology  
But in the future, a combination of design and run-time measures will become necessary in order to guarantee that reliability guidelines are met.  ...  These can for example be caused by high power densities and temperatures. At the moment it is still possible to cope with the posed challenges in an affordable manner.  ...  In the scenario of simple-control, we change to a random frequency and voltage every 10 s of simulation time. Figure 10 shows the resulting frequency and voltage settings.  ... 
doi:10.2197/ipsjtsldm.3.140 fatcat:rjyitucncvb4baj2hzjm5twg7u

Reconfigurable Multiparameter Biosignal Acquisition SoC for Low Power Wearable Platform

Jongpal Kim, Hyoungho Ko
2016 Sensors  
In the proposed approach, however, one AFE can be reconfigured in real time into an EP sensing mode for voltage signals, into an IMP sensing mode for modulated voltage signals, into an EC sensing mode  ...  In the conventional CBIA, however, the reconfigurability is hard to achieve. In this paper, a reconfigurable sensing channel based on the CBIA with multi sensing modalities is presented.  ...  Author Contributions: Jongpal Kim is the first author, and he drafted the manuscript. He also implemented the circuit blocks and designed the top architecture of the IC.  ... 
doi:10.3390/s16122002 pmid:27898004 pmcid:PMC5190983 fatcat:w5h4jvph5vbrpno5hr6otkxowy

First- and second-level packaging for the IBM eServer z900

H. Harrer, H. Pross, T.-M. Winkel, W. D. Becker, H. I. Stoller, M. Yamamoto, S. Abe, B. J. Chamberlin, G. A. Katopis
2002 IBM Journal of Research and Development  
The high-frequency requirements of this design due to operating frequencies of 918 MHz for on-chip and 459 MHz for off-chip interconnects make a comprehensive design methodology and post-routing electrical  ...  In this paper we compare these two technologies and describe their impact on the MCM electrical design.  ...  , East Fishkill, and Endicott, and of the Hitachi packaging department in Hadano.  ... 
doi:10.1147/rd.464.0397 fatcat:6skl6bea2bhc3pzhub2pmzsvmu

Compiler-directed frequency and voltage scaling for a multiple clock domain microarchitecture

Arun Rangasamy, Rahul Nagpal, Y.N. Srikant
2008 Proceedings of the 2008 conference on Computing frontiers - CF '08  
Multiple Clock Domain processors provide an attractive solution to the increasingly challenging problems of clock distribution and power dissipation.  ...  They allow their chips to be partitioned into different clock domains, and each domain's frequency (voltage) to be independently configured.  ...  [26] and [25] , compiler based frequency (voltage) scaling for single clock domain systems, achieve impressive results.  ... 
doi:10.1145/1366230.1366267 dblp:conf/cf/RangasamyNS08 fatcat:235cr66nuzg5lobx3huc33brk4
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