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Minimization of Latency and Power for Network-on-Chip

Abhijeet V.
2015 International Journal on Recent and Innovation Trends in Computing and Communication  
In addition, multiple virtual circuit-switched (VCS) connections are granted to share a common physical channel.  ...  Moreover, a path allocation algorithm is used in this paper to determine VCS connections and circuit-switched connections on a mesh-connected NoC, such that both communication latency and power are optimized  ...  The network with virtual point-to-point (VIP) connections [6] is another hybrid circuit PS scheme for NoCs. A VIP is also a kind of CS connection.  ... 
doi:10.17762/ijritcc2321-8169.150226 fatcat:4mpczef5kbgidjcumcw3g2ynkm

Low Latency NoC Router Micro Architecture using Dynamic Virtual Channel Organization

Praveen M
2017 International Journal for Research in Applied Science and Engineering Technology  
The channel buffer organization of NoC uses virtual channels (VCs) to improve data flow and performance of the NoC system.  ...  To show the advantages of EDVC, we compare its micro-architecture with that of the traditional dynamic VC (CDVC), it's also employs link-list tables for buffer organization.  ...  Traditionally, Integrated Circuits are designed with dedicated point-to-point connections, with one wire dedicated to every signal.  ... 
doi:10.22214/ijraset.2017.4216 fatcat:hdvwoxkzrndhfefomnaynog5bu

Supporting non-contiguous processor allocation in mesh-based CMPs using virtual point-to-point links

M Asadinia, M Modarressi, A Tavakkol, H Sarbazi-Azad
2011 2011 Design, Automation & Test in Europe  
This mechanism targets the on-chip communication and aims to reduce the power and latency of the NoC employed as the communication infrastructure.  ...  connecting them by bypassing the router pipeline stages of the inter-region routers.  ...  Focusing on on-chip communication, we used a hybrid switched NoC in which packet-switching and virtual point-to-point connections are integrated into the same NoC.  ... 
doi:10.1109/date.2011.5763072 dblp:conf/date/AsadiniaMTS11 fatcat:sexhjoibe5evfavim6x67fmvfa

On the Potential of NoC Virtualization for Multicore Chips

Jose Flich, Samuel Rodrigo, Jose Duato, Thomas Sødring, Åshild Grønstad Solheim, Tor Skeie, Olav Lysne
2008 2008 International Conference on Complex, Intelligent and Software Intensive Systems  
The intention behind this paper is for it to serve as a position paper on the topic of virtualization for NoC and the challenges that should be met at the routing layer in order to optimize performance  ...  In particular, we propose the use of virtualization techniques at the NoC level.  ...  Many questions with regard to the design of a virtualized NoC can be posed. Does the virtualized system allow for the merging of different regions?  ... 
doi:10.1109/cisis.2008.97 dblp:conf/cisis/FlichRDSSSL08 fatcat:anxhg6nqkvhjzbd5tr7qfvgp7a

A Survey for Silicon on Chip Communication

K. Ashok Kumar, P. Dananjayan
2017 Indian Journal of Science and Technology  
Findings: This paper proposes a new architecture for low latency and low area NoC router by analyzing the different architectures for NoC by observing the number of architectures.  ...  Objectives: Network on Chip (NoC) has been emerging area as communication is very complex at Chip Multi Processor and it has become more popular due to its high bandwidth and improved performance than  ...  Communication networks are connecting different geographically distributed points. In point to point communication, the connection of the any two resources is fixed.  ... 
doi:10.17485/ijst/2017/v10i1/110286 fatcat:rytgznvryjbc3mau7e5xgkaf6i

The aethereal network on chip after ten years

Kees Goossens, Andreas Hansson
2010 Proceedings of the 47th Design Automation Conference on - DAC '10  
Keywords Network on chip, rate control, circuit switching APPLICATION DOMAIN AND GOALS Work on the AEthereal network on chip (NOC) started at Philips Research, for systems on chip (SOC) in the consumerelectronics  ...  To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specic permission and/or a fee. SOC bandwidth and latency for video and audio processing.  ...  Acknowledgements Many people contributed to AEthereal. We thank them all, especially Jef van Meerbergen.  ... 
doi:10.1145/1837274.1837353 dblp:conf/dac/GoossensH10 fatcat:zbmmxtmmgbdyhixhyyzgzknzpa

The CONNECT Network-on-Chip Generator

Michael K. Papamichael, James C. Hoe
2015 Computer  
Chips with a handful of major modules can still rely on ad hoc point-to-point wires or a shared bus, but such approaches do not scale to the extent needed for current SoC communication needs.  ...  Research papers by CONNECT users have reported employing CONNECT to generate NoCs for design research or for production IP in design projects.  ... 
doi:10.1109/mc.2015.378 fatcat:2tvy7h3r4vgqbgsjj3b5jsqvcm

Traffic Generation and Performance Evaluation for Mesh-based NoCs

Leonel Tedesco, Aline Mello, Diego Garibotti, Ney Calazans, Fernando Moraes
2005 2005 18th Symposium on Integrated Circuits and Systems Design  
The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation.  ...  The main contribution of this work is the set of methods for internal NoC evaluation, which help designers to optimize the network under different traffic scenarios.  ...  The Local port is connected to an IP and the others are connected to neighbor routers. Each port has an input buffer for temporary storage. The switching mode is wormhole.  ... 
doi:10.1109/sbcci.2005.4286854 fatcat:jmhit3okkvggroon7bgp32wdhm

An FPGA bridge preserving traffic quality of service for on-chip network-based systems

A B Nejad, M E Martinez, K Goossens
2011 2011 Design, Automation & Test in Europe  
Moreover, having external access to SoCs for verification and debug purposes is essential.  ...  In this paper, we suggest to partition a network-on-chip (NoC) based system into smaller sub-systems each with their own NoC, and each of which is implemented on a separate FPGA board.  ...  The bus is responsible for handling the distributed shared-memory communications in order to send the request to an specific connection shell (point 2 in the Figure ) .  ... 
doi:10.1109/date.2011.5763074 dblp:conf/date/NejadMG11 fatcat:3fkm7qq5kzhbpjbfokx2vrajne

Traffic generation and performance evaluation for mesh-based NoCs

Leonel Tedesco, Aline Mello, Diego Garibotti, Ney Calazans, Fernando Moraes
2005 Proceedings of the 18th annual symposium on Integrated circuits and system design - SBCCI '05  
The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation.  ...  The main contribution of this work is the set of methods for internal NoC evaluation, which help designers to optimize the network under different traffic scenarios.  ...  The Local port is connected to an IP and the others are connected to neighbor routers. Each port has an input buffer for temporary storage. The switching mode is wormhole.  ... 
doi:10.1145/1081081.1081129 dblp:conf/sbcci/TedescoMGCM05 fatcat:q3qozw7sbndv7dymzzj7czrvwy

Virtual Architectures for partial runtime reconfigurable systems. Application to Network on Chip based SoC emulation

Y.E. Krasteva, E. de la Torre, T. Riesgo
2008 2008 34th Annual Conference of IEEE Industrial Electronics  
The paper presents a method for designing Virtual Architectures (VAs) for partial runtime reconfigurable systems (pRTRs). The presented method permits to create flexible pRTRs.  ...  Such pRTR system is used as a core for a Network on Chip based SoC emulation. The main advantage of the emulation framework is that it permits fast emulation and design space exploration.  ...  ACKNOWLEDGMENT The authors wish to express their gratitude to the Departamento de Fundamentos da Computacao, Pontificia Universidade Catolica do Rio Grande do Sul, specially to Ney Calazans, for providing  ... 
doi:10.1109/iecon.2008.4758347 fatcat:pljvonyew5ed7fd7pqvuxugfbu

An Effective Bidirectional Network on Chip with Pipelining and Self Reconfigurable Channel

A. Rajalingam, Bechtel Brabi
2014 Research Journal of Applied Sciences Engineering and Technology  
The Bi-NoC architecture allows each channel to transmit in all direction and increases the bandwidth, reduces the access latency and reduces power consumption.  ...  The XY routing algorithm is used to perform the architecture.  ...  The benefit of NoC is that multiple point to point link can be connected with the help of the switches.  ... 
doi:10.19026/rjaset.7.856 fatcat:tviqy23ukbeqjndw3vzgpx7fdi

Multiple task migration in mesh network on chips over virtual point-to-point connections

E. Lakshmi Prasad, V. Sivasankaran, V Nagarajan
2012 2012 International Conference on Computing, Communication and Applications  
The proposed system scheme reduces total message latency, total migration latency, total network latency, power saving is achieved compared to the previously proposed task migration strategy for mesh multic  ...  Multiple task migration is a process in network on chips are able to transfer the data from one cluster to another cluster, w transfer the data from one cluster to another cluster message latency, consumption  ...  Conclusion In this paper, we proposed multiple task migration schemes in mesh-based NoCs based on low-latency and low power virtual point-to-point (VIPs) connections.  ... 
doi:10.1109/iccca.2012.6179171 fatcat:durijhrx3zh3npfrgwqau3igrq

A Study Of Recent Contribution On Simulation Tools For Network-On-Chip

Muthana Saleh Alalaki, Michael Opoku Agyeman
2017 Zenodo  
As a result, Network-on-Chip (NoC) has emerged as a system architecture to overcome intra-communication issues. This paper presents a study of recent contributions on simulation tools for NoC.  ...  Furthermore, an overview of NoC is covered as well as a comparison between some NoC simulators to help facilitate research in on-chip communication.  ...  Delay transitions can be used by the data transfer because it has point-to-point connections. Managing the time is difficult.  ... 
doi:10.5281/zenodo.1130378 fatcat:jsrgix7ff5ffhagvixdkz6iotq

Qos concept for scalable MPEG-4 video object decoding on multimedia (NoC) chips

Milan Pastrnak, Peter De With, Jef Meerbergen
2006 IEEE transactions on consumer electronics  
We demonstrate the QoS framework by mapping of an MPEG-4 arbitrary-shaped decoder on a NoC, employing eight ARM cores with specific monitoring features in the network (e.g. AEthereal NoC).  ...  First, we present the possible scalability of an MPEG-4 arbitraryshaped video decoder with respect to computational and communicational resources.  ...  discussion on AEthereal NoC.  ... 
doi:10.1109/tce.2006.273165 fatcat:t7s2xigjjrawtgqhgimbalhzam
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