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Via assignment in single-row routing

J. Bhasker, S. Sahni
1989 IEEE transactions on computers  
We examine the via assignment problem that arises when the single row routing approach to the interconnection problem is used. Some new complexity results and two new heuristics are obtained.  ...  SINGLE ROW ROUTING The single row routing approach to the interconnection problem for multilayer printed circuit boards was proposed by So, [SO74] .  ...  The single row routing approach imposes three restrictions on the routings that realize the net list N.  ... 
doi:10.1109/12.8737 fatcat:rl4a4old2bhotpepgco234ajvi

Via assignment in single row routing [chapter]

Jayaram Bhasker, Sartaj Sahni
1986 Lecture Notes in Computer Science  
We examine the via assignment problem that arises when the single row routing approach to the interconnection problem is used. Some new complexity results and two new heuristics are obtained.  ...  SINGLE ROW ROUTING The single row routing approach to the interconnection problem for multilayer printed circuit boards was proposed by So, [SO74] .  ...  The single row routing approach imposes three restrictions on the routings that realize the net list N.  ... 
doi:10.1007/3-540-17179-7_10 fatcat:zlxr7ze3cfcnfct3mr25yyedme

Single-Row Transformation of Complete Graphs

Shaharuddin Salleh, Stephan Olariu, Bahrom Sanugi, Mohd Ismail Abd Aziz
2005 Journal of Supercomputing  
Single-row routing is a classical technique in the VLSI design that is known to be NP-complete.  ...  In this paper, we present a technique for transforming a complete graph into a single-row routing problem.  ...  In the single-row routing problem, we are given a set of 2m evenly-spaced terminals (pins or vias), t i , for i = 1, 2, . . . , 2m, arranged horizontally from left to right in a single horizontal row called  ... 
doi:10.1007/s11227-005-0184-4 fatcat:7ly6suanprgbtkwwibx3se7mze

RegularRoute

Yanheng Zhang, Chris Chu
2011 Proceedings of the 2011 international symposium on Physical design - ISPD '11  
wirelength, via count, non preferred usage  Concepts  Track: A sequence of grids in preferred routing direction Panel: A collection of tracks in one column/row of G Cells  Panel: A collection  ...   A set of routing tracks inside one panel g p  Objective  Assign as many segments as possible in regular routing patterns  Minimize wirelength via count non-preferred usage  Minimize  ... 
doi:10.1145/1960397.1960410 dblp:conf/ispd/ZhangC11 fatcat:7x4iet4y7bgi3aegcttdl7titu

Design tools for 3-D integrated circuits

Shamik Das, Anantha Chandrakasan, Rafael Reif
2003 Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC  
For example, relative to single-die placement, we observe on average 28% to 51% reduction in total wire length.  ...  Using these tools -a 3-D standard-cell placement tool, global routing tool, and layout editor -we have targeted existing standard-cell circuit netlists for fabrication using wafer bonding.  ...  We therefore limit the total capacity for inter-wafer vias to number a single row's worth of vias per row of cells on a wafer (e.g. if a given wafer has ten rows of cells, and 50 vias can fit side-by-side  ... 
doi:10.1145/1119772.1119783 dblp:conf/aspdac/DasCR03 fatcat:5bls6ewdd5gbxajjmfovi5zaxu

A NEW DYNAMIC SINGLE-ROW ROUTING FOR CHANNEL ASSIGNMENTS

N Patra .
2014 International Journal of Research in Engineering and Technology  
One of the graph theoretic approaches of channel assignment for cellular networks is routing a pair of nodes arranged in a single-row axis called single-row routing problem.  ...  The network with nodes representing caller and receiver is to be transformed into a single-row network efficiently is proposed.  ...  Due to the frequent change in the shape of the graph, channel assignment is performed in the network using a routing method known as dynamic single-row routing.  ... 
doi:10.15623/ijret.2014.0307072 fatcat:tkt55kkednb7hn5dgt6pmwl7tm

MILP-Based Efficient Routing Method with Restricted Route Structure for 2-Layer Ball Grid Array Packages

Yoichi TOMIOKA, Yoshiaki KURATA, Yukihide KOHIRA, Atsushi TAKAHASHI
2009 IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences  
, nearest via assignment, package routing, radiate Yoichi Tomioka received his B.E., M.E., and D.E. degrees from Tokyo Institute of Technology, Tokyo, Japan, in 2005, 2006, and 2009, respectively.  ...  In this paper, we propose a routing method for 2-layer ball grid array packages that generates a routing pattern satisfying a design rule.  ...  Acknowledgments This research was partially supported by Grant-in-Aid for JSPS Fellows (19·9340).  ... 
doi:10.1587/transfun.e92.a.2998 fatcat:b3oaoo2f75fn3m7k3ykktyfcce

On old and new routing problems

Malgorzata Marek-Sadowska
2011 Proceedings of the 2011 international symposium on Physical design - ISPD '11  
A Short History of Interconnect Routing DFM driven routing; dramatic algorithmic improvements. -now Over-the-cell routing, 3D and multilayer placement and routing techniques developed.  ...  Routing + electrical constraints = physical synthesis introduced. -2000 First performance-driven tools , clock routing, power and ground routing; graph theory, computational geometry, algorithm complexity  ...  of conductor pins reaching all layers, or vias What is special about Single Row?  ... 
doi:10.1145/1960397.1960404 dblp:conf/ispd/Marek-Sadowska11 fatcat:mp5gwvyhiveafhkl6ndfcy3w4e

Routability Driven Via Assignment Method for 2-Layer Ball Grid Array Packages

Yoichi TOMIOKA, Atsushi TAKAHASHI
2009 IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences  
In experiments, in most cases, via assignment and global routing on both of layers in which all nets are realized and the violation of wire congestion on layer 1 is small are speedily obtained.  ...  We propose a fast routing method for 2-layer Ball Grid Array packages that iteratively modifies via assignment.  ...  Acknowledgments This research was partially supported by Grant-in-Aid for JSPS Fellows (19·9340).  ... 
doi:10.1587/transfun.e92.a.1433 fatcat:xrq3idpab5de5opbkx6yifuq7i

Single-Row Routing in Narrow Streets

Sanyong Han, S. Sahni
1984 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
We develop fast linear time algorithms for single row routing when the upper and lower street capacities are less than or equal to three.  ...  There are five phases in this decomposition [8], [5): I. Via assignment, ' ) Linear placement of via columns, 3. Layering, 4. Single row routing, 5. Via elimination.  ...  In this paper, we are concerned only with the fourth phase: Single row routing.  ... 
doi:10.1109/tcad.1984.1270080 fatcat:gqm6tpk4cfdcbclyifq6gdoaw4

Standard cell pin access and physical design in advanced lithography

Xiaoqing Xu, Brian Cline, Greg Yeric, David Z. Pan, Andreas Erdmann, Jongwook Kye
2016 Optical Microlithography XXIX  
Standard cell pin access has become one of the most challenging issues for the back-end physical design in sub-14nm technology nodes due to increased pin density, limited number of routing tracks, and  ...  In this paper, we will introduce a holistic approach across different design stages to deal with the pin access issue while accommodating the complex DFM constraints in advanced lithography.  ...  Given a row of standard cells, we build the single row pin access graph as shown in Fig. 8 .  ... 
doi:10.1117/12.2222289 fatcat:6v3p75z3tvg5dcmxt3pq42fqxa

Dynamic routing and wavelength assignment with optical bypass using ring embeddings

Li-Wei Chen, Eytan Modiano
2005 Optical Switching and Networkning Journal  
We consider routing and wavelength assignment in ring, torus, and tree topologies with the twin objectives of minimizing wavelength usage and maximizing optical bypass.  ...  Finally, we give a RWA for trees that embeds a single virtual ring and uses the ring to obtain a RWA that requires no more than P N/2 total wavelengths; this figure is shown to be optimal for balanced  ...  Therefore a route is assigned as follows: (1) from node 6 to node 5 via a local wavelength, (2) from node 5 to node 13 via a bypass wavelength, and (3) from node 13 to node 12 via a local wavelength again  ... 
doi:10.1016/j.osn.2004.10.003 fatcat:qmukq5covngrdcclu6sk2sbh2e

BEAVER: a computational-geometry-based tool for switchbox routing

J.P. Cohoon, P.L. Heck
1988 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
The layerer completes the switchbox by layering wires that have been assigned a location but not yet a layer. BEAVER has successfully routed all of the classic switchboxes.  ...  preferred routing layer.  ...  Their remarks contributed to the quality of discussion in several sections of this paper. The authors are, as always, grateful to J. Cohoon and C. Heck for their support, suggestions, and comments.  ... 
doi:10.1109/43.3208 fatcat:y44fkujyh5gmrazi2rh2thkrfu

Exact combinatorial optimization methods for physical design of regular logic bricks

Brian Taylor, Larry Pileggi
2007 Proceedings - Design Automation Conference  
These restrictions result in the highly regular layout structure illustrated in Figure 1 . It has been shown [9] that designs implemented using such a fabric can offer performance 344 19.2  ...  Results from our prototype tool demonstrate that these optimization methods are quite practical for bricks of typical size found in large-scale designs.  ...  all NMOS transistors lie in a single row near the bottom of the brick (this is akin to the 'single-row' layout style of standard cells). and area equal to that of standard cell-based designs at the 65nm  ... 
doi:10.1145/1278480.1278568 dblp:conf/dac/TaylorP07 fatcat:jp3pgpbugjagjnne2bkv45hnxm

Exact Combinatorial Optimization Methods for Physical Design of Regular Logic Bricks

Brian Taylor, Larry Pileggi
2007 Proceedings - Design Automation Conference  
These restrictions result in the highly regular layout structure illustrated in Figure 1 . It has been shown [9] that designs implemented using such a fabric can offer performance 344 19.2  ...  Results from our prototype tool demonstrate that these optimization methods are quite practical for bricks of typical size found in large-scale designs.  ...  all NMOS transistors lie in a single row near the bottom of the brick (this is akin to the 'single-row' layout style of standard cells). and area equal to that of standard cell-based designs at the 65nm  ... 
doi:10.1109/dac.2007.375184 fatcat:mhz45ax2rbeurlufvt5vgccbxy
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