A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Filters
Very Long Instruction Word architectures and the ELI-512
1983
Proceedings of the 10th annual international symposium on Computer architecture - ISCA '83
Preserved Fulltext
Trace scheduling generates code for machines called Very Long Instruction Word architectures. ...
In Very Long Instruction Word machines, many statically scheduled, tightly coupled, fine-grained operations execute in parallel within a single instruction stream. ...
ACKNOWLEDGEMENTS Invaluable contributions to the ELI design and the Bulldog Partly to reduce the scope of the project and partly because of the the nature of VLIWs, we are limiting ourselves in various ...
doi:10.1145/800046.801649
dblp:conf/isca/Fisher83
fatcat:55vmbcfodvdu3pmfm5bbg3q2k4
Retrospective: very long instruction word architectures and the ELI-512
1998
25 years of the international symposia on Computer architecture (selected papers) - ISCA '98
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
When John Ruttenberg and I laid out the basics of the high-level ELI architecture, we decided that register banks had to be split. ...
This much ILP and weird long instructions to boot; it was too much for most people to accept. ...
doi:10.1145/285930.285945
dblp:conf/isca/Fisher98
fatcat:3bvw3s6v6rdlxn5ktvhis3naka
Very long instruction work architectures and the ELI-512
1998
25 years of the international symposia on Computer architecture (selected papers) - ISCA '98
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Trace scheduling generates code for machines called Very Long Instruction Word architectures. ...
In Very Long Instruction Word machines, many statically scheduled, tightly coupled, fintgrained operations execute in parallel within a single instruction stream. ...
ACKNOWLEDGEMENTS Invaluable contribntions to the ELI design and the Bulldog compiler have been made by John Ruttcnberg, Akxandm Nicolau, John Ellis, Mark Sidell, John O'Donnell, and Charles Marshall. ...
doi:10.1145/285930.285985
dblp:conf/isca/Fisher98a
fatcat:ks7knajpljepnooyrlx65jhami
A VLIW architecture for a trace scheduling compiler
1987
SIGARCH Computer Architecture News
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Abstract Very Long Instruction Word (VLIW) architectures were promised to deliver far more than the factor of two or three that current architectures achieve £rom overlapped execution. ...
A thorough discussion of our approach is beyond the scope of this paper.
Summary and Future Work This paper has introduced the Multiflow TRACE Very-Long-Instruction-Word architecture. ...
doi:10.1145/36177.36201
fatcat:2sc6jk6igjc7lgtccrmg4itwka
A VLIW architecture for a trace scheduling compiler
1988
IEEE transactions on computers
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Abstract Very Long Instruction Word (VLIW) architectures were promised to deliver far more than the factor of two or three that current architectures achieve £rom overlapped execution. ...
A thorough discussion of our approach is beyond the scope of this paper.
Summary and Future Work This paper has introduced the Multiflow TRACE Very-Long-Instruction-Word architecture. ...
doi:10.1109/12.2247
fatcat:ntyyt7kc5vdjdfim55ge6wuf6m
A VLIW architecture for a trace scheduling compiler
1987
SIGPLAN notices
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
Abstract Very Long Instruction Word (VLIW) architectures were promised to deliver far more than the factor of two or three that current architectures achieve £rom overlapped execution. ...
A thorough discussion of our approach is beyond the scope of this paper.
Summary and Future Work This paper has introduced the Multiflow TRACE Very-Long-Instruction-Word architecture. ...
doi:10.1145/36205.36201
fatcat:3tuc4gloqbdzvkrgpkdmbjvt4y
Exposing the mythical MIPS year
1999
Computer
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2010; you can also visit the original URL.
The file type is application/pdf.
But the MIPS year has been classically misapplied and misused as a measurement of the amount of effort needed to break and compare cryptographic keys. ...
Cybersquare MIPS can be a useful measure of processor speed, and MIPS years can be a useful measure of work. ...
As long as you use it as a relative, rather than absolute, measure, and as long as you make the comparisons by running similar types of programs on similar types of architectures, MIPS is a useful measure ...
doi:10.1109/2.781630
fatcat:idjtywz4zff5hplvgmmhi4sasq
Computational Integrity with a Public Random String from Quasi-Linear PCPs
[chapter]
2017
Lecture Notes in Computer Science
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2016; you can also visit the original URL.
The file type is application/pdf.
To quote from the recent authoritative survey [WB15], the reason for this was that "the proofs arising from the PCP theorem (despite asymptotic improvements) were so long and complicated that it would ...
have taken thousands of years to generate and check them, and would have needed more storage bits than there are atoms in the universe". ...
The research reported here has received funding from the following sources, sorted alphabetically: the Center for Science of ...
doi:10.1007/978-3-319-56617-7_19
fatcat:hmijsu5oybgcddlw6eyf2532ja
ELIS++: a shapelet learning approach for accurate and efficient time series classification
2021
World wide web (Bussum)
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2021; you can also visit the original URL.
The file type is application/pdf.
We conduct extensive experiments on 35 UCR datasets, and results verify the effectiveness and efficiency of ELIS++. ...
To learn the higher quality shapelets, based on the PAA shapelet candidates search technique proposed in ELIS, ELIS++ first propose a novel entropy-based approach shapelet candidate selection mechanism ...
We utilize the ubiquitous Single Instruction Multiple Data (SIMD) architecture, which assigns multiple threads to process the same set of instructions on multiple data. ...
doi:10.1007/s11280-020-00856-1
fatcat:u2baj4rncvhujckyocfnvjptaa
Record Setting Software Implementation of DES Using CUDA
2010
2010 Seventh International Conference on Information Technology: New Generations
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
The key point is to assess how well the structure of a symmetric key cipher can fit the GPU programming model and the single instruction multiple data architectural parallelism. ...
the multi-core Nvidia GT200 graphic architecture. ...
Acknowledgements This work was partially supported by MIUR in the framework of the PRIN SESAME project. ...
doi:10.1109/itng.2010.43
dblp:conf/itng/AgostaBSP10
fatcat:put2eqy7lzeglczkipdlkbgs7m
Transparent Harddisk Encryption
[chapter]
2001
Lecture Notes in Computer Science
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2011; you can also visit the original URL.
The file type is application/pdf.
This paper introduces a new block cipher, and discusses its security. Its design is optimized for high-bandwidth applications that do not have high requirements on key-schedule latency. ...
Optimization of the code on the 21264 architecture is still undergoing work. To the very least, "64 rounds" is a conservative number, in a security point of view. ...
The 21164 can issue up to four instructions in each cycle, but only two load/store instructions and two logical instructions. ...
doi:10.1007/3-540-44709-1_23
fatcat:3knjt37e2za55bjzuukzrwyixa
Predicting conditional branch directions from previous runs of a program
1992
Proceedings of the fifth international conference on Architectural support for programming languages and operating systems - ASPLOS-V
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
The file type is application/pdf.
"Very
long instruction
word
architectures
and the ELI-5 12," Proceedings
of the 10th
Annual
International
Symposium
on
Computer
Architecture,
pp. 140-150, [Johnson 91]
W. Johnson. ...
for the long instruction produced tiom several operations. ...
doi:10.1145/143365.143493
dblp:conf/asplos/FisherF92
fatcat:swulukeehndd5bpbwgwihijx6m
Computer vision algorithms on reconfigurable logic arrays
1999
IEEE Transactions on Parallel and Distributed Systems
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2011; you can also visit the original URL.
The file type is application/pdf.
Ratha Computer vision algorithms are natural candidates for high performance computing due to their inherent parallelism and intense computational demands. For ...
Tredennick 219] has suggested the following three ways to improve the performance of present d a y uniprocessors: (i) superscalar, (ii) multiprocessing, and (iii) use of very long instruction word (VLIW ...
Yet another way to classify the architectures is based on the instruction and data streams. ...
doi:10.1109/71.744833
fatcat:htpcqypklnghvfdedyl7dneyhu
A fast new DES implementation in software
[chapter]
1997
Lecture Notes in Computer Science
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
The file type is application/pdf.
The expansion and permutation operations: these operations do not cost any operation, since instead of changing the order of words (or duplicating words), we can address the required word directly. ...
This implementation uses a non-standard representation, and view the processor as a SIMD computer, i.e., as 64 parallel one-bit processors computing the same instruction. ...
Acknowledgements We are grateful to Adi Shamir, Ross Anderson and the referees for their various remarks and suggestions that improved the results and exposition of this paper. ...
doi:10.1007/bfb0052352
fatcat:m6eehbnyjzhrfjsv3daiq2elsy
An implementation of a code generator specification language for table driven code generators
1982
Proceedings of the 1982 SIGPLAN symposium on Compiler construction - SIGPLAN '82
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
The file type is application/pdf.
We successfully replaced the hand written code generator of an existing compiler with one which was produced automatically from a formal specification. ...
}
where word, iadd and store are operators in
the IF. ...
The
problem
of
long
and
short
instruction
sizes
[9,10]
(and
hence
the
absolute
size
of the
3 Actually every LHS
is
prefixed
to
the
input stream. ...
doi:10.1145/800230.806979
dblp:conf/sigplan/Bird82
fatcat:nshvkbyn2va4feeuqimn4mshq4
« Previous
Showing results 1 — 15 out of 672 results