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RTL c-based methodology for designing and verifying a multi-threaded processor

Luc Sèmèria, Renu Mehra, Barry Pangrle, Arjuna Ekanayake, Andrew Seawright, Daniel Ng
2002 Proceedings - Design Automation Conference  
The methodology is centered on statically scheduled C-based coding style, C to HDL translation, and a novel RTL-C to RTL-Verilog equivalence checking flow.  ...  It leverages improved simulation performance combined with static techniques to reduce the amount of RTL-Verilog and gate-level verification required during development.  ...  The definition of this design methodology involved the work of several members of the design and verification teams.  ... 
doi:10.1145/513918.513951 dblp:conf/dac/SemeriaMPESN02 fatcat:3w7rm3b2yrg7ljvc2uc5rkyeha

RTL c-based methodology for designing and verifying a multi-threaded processor

Luc Sèmèria, Renu Mehra, Barry Pangrle, Arjuna Ekanayake, Andrew Seawright, Daniel Ng
2002 Proceedings - Design Automation Conference  
The methodology is centered on statically scheduled C-based coding style, C to HDL translation, and a novel RTL-C to RTL-Verilog equivalence checking flow.  ...  It leverages improved simulation performance combined with static techniques to reduce the amount of RTL-Verilog and gate-level verification required during development.  ...  The definition of this design methodology involved the work of several members of the design and verification teams.  ... 
doi:10.1145/513950.513951 fatcat:s3h3m2nudjfitphlzfkubh4mvq

RTL C-based methodology for designing and verifying a multi-threaded processor

L. Semeria, A. Seawright, R. Mehra, D. Ng, A. Ekanayake, B. Pangrle
2002 Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)  
The methodology is centered on statically scheduled C-based coding style, C to HDL translation, and a novel RTL-C to RTL-Verilog equivalence checking flow.  ...  It leverages improved simulation performance combined with static techniques to reduce the amount of RTL-Verilog and gate-level verification required during development.  ...  The definition of this design methodology involved the work of several members of the design and verification teams.  ... 
doi:10.1109/dac.2002.1012606 fatcat:2otw277idfbg7lcekm6vlecmhm

Formally Verifying WARP-V, an Open-Source TL-Verilog RISC-V Core Generator [article]

Steven Hoover, Ákos Hadnagy
2018 arXiv   pre-print
Our primary verification vehicle for WARP-V was a formal verification framework for RISC-V, called riscv-formal.  ...  The timing-abstract and transaction-level logic modeling techniques of TL-Verilog greatly simplified the task of creating a harness connecting the WARP-V model to the verification interface of riscv-formal  ...  This paper presents the first real-world use of TL-Verilog for verification modeling and shows how the flexibility benefits of TL-Verilog modeling extend into verification.  ... 
arXiv:1811.12474v1 fatcat:n7kz46ompzc5vkd5zk3b22x42a

An FPGA design and implementation framework combined with commercial VLSI CADs

Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2013 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)  
GDS Formal Verification Formal Verification FPGA CADs Kumamoto University Fast evaluation with EasyRouter Synthesis Layout STA Tile HDL code EasyRouter (Fast performance analysis  ...  ) • Not for synthesizable FPGA • Delay model is not suitable for standard cells based design Kumamoto University • Only support "Island Style" FPGA • Parameters can be changed in XML based  ...  Thank you for your attention.  ... 
doi:10.1109/recosoc.2013.6581534 dblp:conf/recosoc/ZhaoAIKS13 fatcat:hklltatlifghnj5our2e3n2fhy

On embedding a hardware description language in Isabelle/HOL

Wilayat Khan, David Sanan, Zhe Hou, Liu Yang
2019 Design automation for embedded systems  
In order to define executable hardware description language while at the same time be fit for formal proofs of properties, a hardware description language VeriFormal, embedded in Isabelle/HOL, was created  ...  Among the main features of VeriFormal include formal semantics of the language, support for mechanical reasoning about designs and compiler and type checking of modules using Isabelle/HOL as well as VeriFormal  ...  Circuit Verification in VeriFormal The main motivation for creating VeriFormal was to support formal verification of hardware descriptions described in HDL Verilog.  ... 
doi:10.1007/s10617-019-09226-1 fatcat:gyvbq6ijczf4voaqvvqlqylpae

Impact of Description Language, Abstraction Layer, and Value Representation on Simulation Performance

Wolfgang Ecker, Volkan Esen, Lars Schonberg, Thomas Steininger, Michael Velten, Michael Hull
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
We found that Verilog is on average 2x faster than VHDL for RTL models.  ...  For the presented analysis, we considered five designs that have been modeled in VHDL, Verilog, SystemVerilog, and SystemC, using different value representations and coding styles, covering the abstraction  ...  The main reason is that simulation is still the workhorse for verification despite the upcoming of formal methods, emulation, and FPGA prototyping.  ... 
doi:10.1109/date.2007.364688 dblp:conf/date/EckerESSVH07 fatcat:ntq7va7lezdu7hc536ge4am54e

Use of Formal Verification at Centaur Technology [chapter]

Warren A. Hunt, Sol Swords, Jared Davis, Anna Slobodova
2010 Design and Verification of Microprocessor Systems for High-Assurance Applications  
Overview of Verification Methodology In our verification process, we first translate the Verilog RTL source code of Centaur's design into EMOD, a formally defined HDL.  ...  We verify Verilog designs by first translating them into a formally defined hardware description language, and then using a variety of automated verification algorithms controlled by theorem-proving scripts  ...  We would also like to thank Bob Boyer for development of much of the technology behind EMOD and the ACL2 BDD package, Terry Parks for developing a very detailed floating-point addition specification, and  ... 
doi:10.1007/978-1-4419-1539-9_3 fatcat:qczrzp6ah5a5lmq75hllk6oymq

Design and Verification Languages [chapter]

Stephen Edwards
2016 Electronic Design Automation for IC System Design, Verification, and Testing  
extension of Verilog; and OpenVera, e, and PSL, the three leading contenders for becoming the main verification language.  ...  These have been designed to assist in a simulation-based or formal verification process by providing mechanisms for checking temporal properties, generating pseudorandom test cases, and for checking how  ...  Figure 1 shows the various modeling styles supported in Verilog.  ... 
doi:10.1201/b19569-20 fatcat:qx7qryj7rzaczkr35dvyfujboe

Design and Verification Languages [chapter]

Stephen Edwards
2006 Industrial Information Technology  
extension of Verilog; and OpenVera, e, and PSL, the three leading contenders for becoming the main verification language.  ...  These have been designed to assist in a simulation-based or formal verification process by providing mechanisms for checking temporal properties, generating pseudorandom test cases, and for checking how  ...  Figure 1 shows the various modeling styles supported in Verilog.  ... 
doi:10.1201/9781420007947.sec4 fatcat:gct26kctovf7jarotiwzaagd3u

Assertion Based Functional Verification of March Algorithm Based MBIST Controller [article]

Ashwani Kumar
2021 arXiv   pre-print
In assertion based functional verification, creation of verification plan, for MBIST controller RTL model and the implementation & simulation of the verification plan using System-Verilog and Synopsys-VCS  ...  Assertions are used to check the errors in RTL model of MBIST controller and to provide the functionality coverage. Functional coverage metrics are used to track the level or quality of verification.  ...  Formal Verification alone cannot be the complete solution for design verification with the existing limitations in design style as it is shown in Figure 1 .3 that formal verification has less number of  ... 
arXiv:2106.11461v1 fatcat:4q37rfbswrc3fe66logyqlfp2m

An approach to Verilog-VHDL interoperability for synchronous designs [chapter]

Dominique Borrione, Fredrik Vestman, Hakim Bouamama
1997 IFIP Advances in Information and Communication Technology  
This common semantic model can be used as a kernel for cycle-based simulation, formal verification, and synthesis, irrespective of the source language.  ...  This paper suggests that synchronous designs written in either Verilog or VliDL can be interpreted in tenns of a common Hierarchical Finite State Machine model, and shows the principles for extracting  ...  Berkeley for their friendly cooperation, and their kind help concerning the VIS system and the vl2mv compiler.  ... 
doi:10.1007/978-0-387-35190-2_5 fatcat:mgys22yk55f4jdrkqodlhctj2q

A Tool for Checking ANSI-C Programs [chapter]

Edmund Clarke, Daniel Kroening, Flavio Lerda
2004 Lecture Notes in Computer Science  
We present a tool for the formal verification of ANSI-C programs using Bounded Model Checking (BMC).  ...  This is essential for presenting long counterexample traces: the tool allows stepping through the trace in the same way a debugger allows stepping through a program.  ...  We hope to make formal verification tools accessible to non-expert users this way. Hardware Verification using ANSI-C as a Reference.  ... 
doi:10.1007/978-3-540-24730-2_15 fatcat:75ka5bhqcbayxpxli2qffrr6eu

A pointcut-based assertion for high-level hardware design

Yusuke Endoh, Takeo Imai, Mikito Iwamasa, Yoshio Kataoka
2008 Proceedings of the 2008 AOSD workshop on Aspects, components, and patterns for infrastructure software - ACP4IS '08  
We show that the model is useful for making pointcut-based assertion more robust.  ...  Since conventional assertion languages are for conventional HDLs, they only allow specification of change of variables or low-level events raised along with signals.  ...  The model in SpecC is more abstract than the one in Verilog HDL (e.g., clock does not show up at all in SpecC model).  ... 
doi:10.1145/1404891.1404895 fatcat:4r52eyxysbhzvjvtk6hmle5btm

Verilog HDL and its ancestors and descendants

Peter Flake, Phil Moorby, Steve Golson, Arturo Salz, Simon Davidmann
2020 Proceedings of the ACM on Programming Languages (PACMPL)  
For large-scale digital logic design, previous schematic-based techniques have transformed into textual registertransfer level (RTL) descriptions written in Verilog.  ...  Shepherd: Keshav Pingali, University of Texas at Austin, USA This paper describes the history of the Verilog hardware description language (HDL), including its influential predecessors and successors.  ...  An important aspect of formal property verification tools is that their proofs are exhaustive. They do not rely on the simulation of the HDL code, and thus require no testbench.  ... 
doi:10.1145/3386337 fatcat:ttezkcr6pzgppbeofpi23vu2wy
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