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Verifying x86 Instruction Implementations
[article]
2019
arXiv
pre-print
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To our knowledge, there are no similar results in the verification of implementations of an x86 microprocessor. ...
We focus on proving correctness of instruction implementations, which includes the decoding of an instruction, its translation into a sequence of micro-operations, any subsequent execution of traps to ...
We use the ACL2 theorem prover [2] and built-in verified proof routines [37, 35] to model and verify a target RTL implementation of instruction execution. ...
arXiv:1912.10285v1
fatcat:aeocsrtb5zd6vfsqklcoi3stxy
Steps towards Verified Implementations of HOL Light
[chapter]
2013
Lecture Notes in Computer Science
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x86)
(approx. 7000 64-bit x86 instructions)
semantics of Milawa's logic
inference rules of Milawa's logic
Lisp semantics
semantics of x86-64 machine
Milawa theorem prover
(kernel approx. ...
Cambridge)
verified compilation from
CakeML to bytecode
operational semantics
verified type inference
verified parsing (syntax is
compatible with SML)
verified x86 implementations
proof-producing ...
Main message of the talk: We are working towards a verified implementation of ML (called CakeML) A verified HOL light is an initial challenge case study for CakeML. ...
doi:10.1007/978-3-642-39634-2_38
fatcat:4m4fkze4bnazpgmtpuux5w5yiu
CakeML
2014
Proceedings of the 41st ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages - POPL '14
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Step 3: production of verified x86-64 code
Verified x86-64 Implementation Real executable also has 30-line unverified C wrapper. ...
Translation into x86-64 representation of bytecode states, we define a function that maps CakeML Bytecode instructions into concrete x86-64 machine instructions (i.e. lists of bytes). ...
Top-level Correctness Theorem The top-level theorem for the entire x86-64 implementation is stated as follows. Theorem 25 (x86-64 Implementation of REPL s ). ...
doi:10.1145/2535838.2535841
dblp:conf/popl/KumarMNO14
fatcat:esfxvt5fsbd7pnmkgv7izvmh3u
Verified just-in-time compiler on x86
2010
SIGPLAN notices
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Our semantics includes a model of the instruction cache. ...
Two versions of the verified JIT compiler are presented: one generates all of the machine code at once, the other one is incremental i.e. produces code on-demand. ...
For this we needed verified x86 code which implements code generation i.e. translation from bytecode to x86 code. ...
doi:10.1145/1707801.1706313
fatcat:cqgvad6tqzatja2epk6trxxhyi
Verified just-in-time compiler on x86
2010
Proceedings of the 37th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages - POPL '10
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Our semantics includes a model of the instruction cache. ...
Two versions of the verified JIT compiler are presented: one generates all of the machine code at once, the other one is incremental i.e. produces code on-demand. ...
For this we needed verified x86 code which implements code generation i.e. translation from bytecode to x86 code. ...
doi:10.1145/1706299.1706313
dblp:conf/popl/Myreen10
fatcat:uy55r3z3sbclnbbaeqq7nxdxgq
Proof Pearl: A Verified Bignum Implementation in x86-64 Machine Code
[chapter]
2013
Lecture Notes in Computer Science
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The case study we describe is the construction of an x86-64 implementation of arbitrary-precision integer arithmetic. ...
The work presented in this paper has been developed in the HOL4 theorem prover and the case study resulted in 700 lines of verified 64-bit x86 machine code. ...
-The proofs presented in this paper have produced a reusable verified x86-64 implementation of bignum integer operations. ...
doi:10.1007/978-3-319-03545-1_5
fatcat:vwdjj3wqfrdy5lwusekyndhkiu
ISboxing: An Instruction Substitution Based Data Sandboxing for x86 Untrusted Libraries
[chapter]
2015
IFIP Advances in Information and Communication Technology
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Our substitution-based method does not insert any additional instructions into library code and therefore incurs almost no measurable runtime overhead. ...
In this paper, we propose an efficient and practical data sandboxing approach (called ISboxing) on contemporary x86 platforms, which sandboxes a memory read/write by directly substituting it with a selfsandboxed ...
In our current implementation, the verifier is self-contained and takes about 2.5k LOC, most of which are interpretation for x86 opcode decoding. ...
doi:10.1007/978-3-319-18467-8_26
fatcat:ghssrfvktzeqzko6s4k5g7zi64
Language-independent sandboxing of just-in-time compilation and self-modifying code
2011
Proceedings of the 32nd ACM SIGPLAN conference on Programming language design and implementation - PLDI '11
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We have added our extensions to both the x86-32 and x86-64 variants of a production-quality, SFI-based sandboxing platform; on those two architectures SFI mechanisms face different challenges. ...
A number of implementation challenges were specific to x86-64. ...
The x86-64 implementation of Native Client uses the ILP32 data model, to facilitate source code portability between x86-32 and x86-64 sandboxes. ...
doi:10.1145/1993498.1993540
dblp:conf/pldi/AnselMETCSSBY11
fatcat:pbd33aeclredjkepisl7rfgkyy
Language-independent sandboxing of just-in-time compilation and self-modifying code
2011
SIGPLAN notices
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We have added our extensions to both the x86-32 and x86-64 variants of a production-quality, SFI-based sandboxing platform; on those two architectures SFI mechanisms face different challenges. ...
A number of implementation challenges were specific to x86-64. ...
The x86-64 implementation of Native Client uses the ILP32 data model, to facilitate source code portability between x86-32 and x86-64 sandboxes. ...
doi:10.1145/1993316.1993540
fatcat:lem3mp6kdzff7mnjyy44nbrhzu
Language-independent sandboxing of just-in-time compilation and self-modifying code
2012
SIGPLAN notices
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We have added our extensions to both the x86-32 and x86-64 variants of a production-quality, SFI-based sandboxing platform; on those two architectures SFI mechanisms face different challenges. ...
A number of implementation challenges were specific to x86-64. ...
The x86-64 implementation of Native Client uses the ILP32 data model, to facilitate source code portability between x86-32 and x86-64 sandboxes. ...
doi:10.1145/2345156.1993540
fatcat:nl6wtq7btbajll3emqmwuxjk2y
Verified peephole optimizations for CompCert
2016
Proceedings of the 37th ACM SIGPLAN Conference on Programming Language Design and Implementation - PLDI 2016
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Peek contributes four new components: a lower level semantics for CompCert x86 syntax, a liveness analysis, a library for expressing and verifying peephole optimizations, and a verified peephole optimization ...
The approach scans an assembly program for a sequence of instructions matching a syntactic template and replaces it with a faster, equivalent sequence. ...
However, a single extended shift instruction is bitwise equivalent to these three. We implemented and verified two peepholes of this style, but with different orders of shifts. ...
doi:10.1145/2908080.2908109
dblp:conf/pldi/MullenZTG16
fatcat:4nth3jj23ndjdnoeu7n5bfrzou
Verified peephole optimizations for CompCert
2016
SIGPLAN notices
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Peek contributes four new components: a lower level semantics for CompCert x86 syntax, a liveness analysis, a library for expressing and verifying peephole optimizations, and a verified peephole optimization ...
The approach scans an assembly program for a sequence of instructions matching a syntactic template and replaces it with a faster, equivalent sequence. ...
However, a single extended shift instruction is bitwise equivalent to these three. We implemented and verified two peepholes of this style, but with different orders of shifts. ...
doi:10.1145/2980983.2908109
fatcat:z3jh5bnk25bm3j2poeejjjl5vm
Efficient binary translation system with low hardware cost
2009
2009 IEEE International Conference on Computer Design
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These supports are implemented in Godson-3 processors to speedup the x86 binary translation to the native MIPS instruction set. ...
To verify the thoughts, the XBAR (X86 Binary translation Acceleration on RISC processors) system is designed and implemented based on Godson [9] [10], a MIPS64 compatible processor. ...
The logic design work of the new x86 decode unit is also easy to be done and verified. ...
doi:10.1109/iccd.2009.5413138
dblp:conf/iccd/HuLWCSL09
fatcat:egk54du44fgs7evfqamr2evehe
Scalable validation of binary lifters
2020
Proceedings of the 41st ACM SIGPLAN Conference on Programming Language Design and Implementation
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The semantics faithfully formalizes all the non-deprecated, sequential user-level instructions of the x86-64 Haswell instruction set architecture. ...
The translation validation of instructions in isolation revealed 29 new bugs in McSema -a mature open-source lifter from x86-64 to LLVM IR. ...
We present the actual specification that is fed to the x86-64 verifier. ...
doi:10.1145/3385412.3385964
dblp:conf/pldi/DasguptaDVAF20
fatcat:3khjl5gbmnetjay23fk3sc2ktu
The x86isa Books: Features, Usage, and Future Plans
2017
Electronic Proceedings in Theoretical Computer Science
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Note that this fulltext copy is not of the "primary" version of this work. The version it corresponds to is:
2017 pre-print arXiv:1705.01225v1 fatcat:2fp2dwgjhbdmxemtjb6hh3w3xa
The x86isa library, incorporated in the ACL2 community books project, provides a formal model of the x86 instruction-set architecture and supports reasoning about x86 machine-code programs. ...
However, analyzing x86 programs can be daunting -- even for those familiar with program verification, in part due to the complexity of the x86 ISA. ...
implement an ISA-level instruction. ...
doi:10.4204/eptcs.249.1
fatcat:2iajdpymvfcgfg3haozk4fod24
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