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Verifying and Synthesizing Constant-Resource Implementations with Types

Van Chan Ngo, Mario Dehesa-Azuara, Matthew Fredrikson, Jan Hoffmann
2017 2017 IEEE Symposium on Security and Privacy (SP)  
We propose a novel type system for verifying that programs correctly implement constant-resource behavior.  ...  Finally, we show how our type inference algorithm can be used to synthesize a constant-time implementation from one that cannot be verified as secure, effectively repairing insecure programs automatically  ...  (VeriQ), and by a Google Research Award.  ... 
doi:10.1109/sp.2017.53 dblp:conf/sp/NgoDFH17 fatcat:j2e6usxfefcwje5pvg26iiu2zy

Verifying and Synthesizing Constant-Resource Implementations with Types [article]

Van Chan Ngo, Mario Dehesa-Azuara, Matthew Fredrikson, Jan Hoffmann
2018 arXiv   pre-print
We propose a novel type system for verifying that programs correctly implement constant-resource behavior.  ...  Finally, we show how our type inference algorithm can be used to synthesize a constant-time implementation from one that cannot be verified as secure, effectively repairing insecure programs automatically  ...  IMPLEMENTATION AND EVALUATION Type Inference: Type inference for the constant resource and lower bound systems are implemented in [21] .  ... 
arXiv:1801.01896v1 fatcat:752yxopxinfrfehv3nzgxelf54

Overview of high level synthesis tools

Spyridon Georgakakis, John Evans
2011 Journal of Instrumentation  
It makes a comparison between the different approaches and highlights their advantages and limitations. We also present a high level synthesis example.  ...  High Level Synthesis takes an abstract behavioural or algorithmic description of a digital system and creates a register transfer level structure that realises the described behaviour.  ...  Acknowledgments The authors would like to thank Greg Iles (Imperial College, London) and Andrew Rose (Imperial College, London) for providing the original sorting design and their appreciated input for  ... 
doi:10.1088/1748-0221/6/02/c02005 fatcat:sh5fl45e3jerhhruobt2zjxvhm

Seamless Signal Processing Block Implementation Using the Cubed-C Design Environment

Michael Dossis
2017 International Robotics & Automation Journal  
Design environments and automated CAD systems are proliferated nowadays with various preferences and restrictions in their work environments.  ...  Here the Cubed-C environment is used for the rapid implementation of a number of low level functions and blocks such as UARTs without difficulty.  ...  This type of coding avoids the constant component and offers excellent synchronization of the receiver.  ... 
doi:10.15406/iratj.2017.02.00029 fatcat:7zpbc5ibfrgelgfiqfed33a3me

Enforcing architectural contracts in high-level synthesis

Nikhil Patil, Ankit Bansal, Derek Chiou
2011 Proceedings of the 48th Design Automation Conference on - DAC '11  
We describe a prototype compiler that generates control required to enforce the contract, and thus, synthesizes the pair of descriptions to hardware.  ...  We present a high-level synthesis technique that takes as input two orthogonal descriptions: (a) a behavioral architectural contract between the implementation and the user, and (b) a microarchitecture  ...  We are greatly indebted to the anonymous reviewers for their comments and corrections.  ... 
doi:10.1145/2024724.2024909 dblp:conf/dac/PatilBC11 fatcat:plrfokf3wnaobf4rd5l7cevqim

A method to derive application-specific embedded processing cores

Olivier Hébert, Ivan C. Kraljic, Yvon Savaria
2000 Proceedings of the eighth international workshop on Hardware/software codesign - CODES '00  
These soft cores are not tightly coupled with the target application, and this leads to processing cores sub-optimal for their specific applications.  ...  We present the tool used to perform the analysis of the resources used by an application, and results from a real-world case. Then, various optimization methods are described.  ...  This paper presents the resource wasting problem associated with the direct implementation of a core for SOC, and a set of experiments on application-specific derivation of cores on which this kind of  ... 
doi:10.1145/334012.334029 dblp:conf/codes/HebertKS00 fatcat:ud5bk6hxk5ftxevtg3bmufcuvy

Automated Synthesis of Secure Platform Mappings [chapter]

Eunsuk Kang, Stéphane Lafortune, Stavros Tripakis
2019 Lecture Notes in Computer Science  
In this paper, we introduce the problem of synthesizing a property-preserving platform mapping: synthesize a set of implementation decisions ensuring that a desired property is preserved from a highlevel  ...  OAuth 1.0 and 2.0.  ...  The verifier implements function verify(C, P, Q, Φ) which returns OK if and only if every mapping allowed by constraint C is valid with respect to P, Q, Φ. Generalization Algorithm.  ... 
doi:10.1007/978-3-030-25540-4_12 fatcat:p3c2mbdz65adrkypeh7deftlvy

FPGA implementations of HEVC Inverse DCT using high-level synthesis

Ercan Kalali, Ilker Hamzaoglu
2015 2015 Conference on Design and Architectures for Signal and Image Processing (DASIP)  
Using HLS tools significantly reduced the FPGA development time, and the resulting FPGA implementations achieved real-time performance.  ...  Recently, commercial and academic high-level synthesis (HLS) tools are started to be successfully used for FPGA implementations of digital signal processing algorithms.  ...  with constants are implemented using addition and shift operations), for each TU size and for all TU sizes are given in Table II .  ... 
doi:10.1109/dasip.2015.7367262 dblp:conf/dasip/KalaliH15 fatcat:lljq3llam5fkvdoqgtx732bwxq

Chlorophyll

Phitchaya Mangpo Phothilimthana, Tikhon Jelvis, Rohin Shah, Nishant Totla, Sarah Chasins, Rastislav Bodik
2013 Proceedings of the 35th ACM SIGPLAN Conference on Programming Language Design and Implementation - PLDI '14  
We show that the synthesized programs are no more than 19% slower than highly optimized expert-written programs on the MD5 benchmark and are faster than programs produced by a heuristic, non-synthesizing  ...  of no more than 256 instructions and 64 words of data.  ...  We achieve these goals by extending a simple type system with a partition type and optimally inferring unspecified partitions with our partitioning synthesizer.  ... 
doi:10.1145/2594291.2594339 dblp:conf/pldi/PhothilimthanaJSTCB14 fatcat:kxqmfqg275cevdfxcennhbi6sq

Linking codesign and reuse in embedded systems design

M. Meerwein, C. Baumgartner, W. Glauert
2000 Proceedings of the eighth international workshop on Hardware/software codesign - CODES '00  
Special emphasis has been put on satisfying the requirements of industrial design practice and on the technical and economic constraints associated with automotive control applications.  ...  This paper presents a complete codesign environment for embedded systems which combines automatic partitioning with reuse from a module database.  ...  The PARAMS table contains the names and data types of parameters (input/output variables, constants) associated with the module.  ... 
doi:10.1145/334012.334030 dblp:conf/codes/MeerweinBG00 fatcat:35k6pk5ufnh63hswlttypafyp4

Synthesis of Custom Hardware from ADA with Artificial Intelligence Techniques

Michael Dossis
2013 Advances in Robotics & Automation  
These intelligent techniques include RDF (Resource Description Framework) and logic relations, along with automatic implementation options and they are employed for the transformations of a hardware compiler  ...  These intelligent and formal techniques make the whole transformation from source code to implementation, formal.  ...  The initial ADA specification model is compiled with the GNU ADA and the generated binaries are verified with the ADA testbench and test vectors.  ... 
doi:10.4172/2168-9695.1000121 fatcat:6vwlruh4yfg2bi6dhyhmz2uoy4

The VLSI High-Level Synthesis for Building Onboard Spacecraft Control Systems [chapter]

O. V. Nepomnyashchiy, I. V. Ryjenko, V. V. Shaydurov, N. Y. Sirotinina, A. I. Postnikov
2017 Proceedings of the Scientific-Practical Conference "Research and Development - 2016"  
An offered intermediate representation of VLSI architecture in the form of a control-flow graph and a data-flow graph provides an opportunity for synthesizing circuits and verifying projects on the stage  ...  Modular-network architectures implemented on the "system-on-chip" hardware platform provide required characteristics of onboard control systems.  ...  Acknowledgements Researches are carried out with the financial support of the state represented by the Ministry of Education and Science of the Russian Federation.  ... 
doi:10.1007/978-3-319-62870-7_25 fatcat:trwi3t75fvcslom3co5ziyxgpy

Automated Synthesis of Secure Platform Mappings [article]

Eunsuk Kang, Stephane Lafortune, Stavros Tripakis
2018 arXiv   pre-print
We describe our prototype implementation, and a real-world case study demonstrating the application of our technique to synthesizing secure mappings for the popular web authorization protocols OAuth 1.0  ...  We provide a formalization of the synthesis problem and propose a technique for synthesizing a mapping based on symbolic constraint search.  ...  Acknowledgements This work was partially supported by the NSF SaTC award "Bridging the Gap between Protocol Design and Implementation through Automated Mapping" (CNS-1801546), the NSF Breakthrough award  ... 
arXiv:1705.03618v3 fatcat:kgcs7wqyurelfpw2ut64sxgjsa

FFT Spectrum Analyzer using Goertzel Filter

N. Kalaiarasi, Sahitya Bhoumik
2012 International Journal of Applied Information Systems  
The structure and chronological procedure followed focuses on the sophisticated DSP design and implementation of a Fast Fourier Transform (FFT) spectrum analyzer.  ...  The entire system was implemented in MATLAB Simulink Xilinx System generator (SG) toolbox. After simulation, the verilog coding was extracted and implemented on FPGA Virtex II device.  ...  The direct digital synthesizer acts as digital mixer. The RAM used is two types, distributed memory or block memory.  ... 
doi:10.5120/ijais12-450706 fatcat:2nss6oyrwfckfav4llpcxc4jrm

High assurance SPIRAL

Franz Franchetti, Aliaksei Sandryhaila, Jeremy R. Johnson, Ivan Kadar
2014 Signal Processing, Sensor/Information Fusion, and Target Recognition XXIII  
High Assurance SPIRAL is a scalable methodology to translate a high level specification of a high assurance controller into a highly resource-efficient, platform-adapted, verified control software implementation  ...  Combined with a verified/certified compiler, High Assurance SPIRAL provides a comprehensive complete solution to the efficient synthesis of verifiable high assurance controllers.  ...  Our system provides a framework to verify various types of rules needed, and the verification of rule application during a rewriting process.  ... 
doi:10.1117/12.2053974 fatcat:o5acta5sknfhbocrdh6rnqxqhi
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