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An integrated functional performance simulator

C. Bechem, J. Combs, N. Utamaphethai, B. Black, R.D.S. Blanton, J.P. Shen
1999 IEEE Micro  
Acknowledgments Our research was supported in part by ONR (N00014-95-1-1112 and N00014-96-1-0347) and by Intel.  ...  O ur new fMW tool will be the workhorse for our future research on advanced microarchitecture techniques.  ...  Direct simulation of mispredicted path instructions and value prediction mechanisms could then be supported. Such a simulation tool can also be used to validate speculation and recovery mechanisms.  ... 
doi:10.1109/40.768499 fatcat:54ekffsosvdehbzrvcwsggv74q

Microprocessors — 10 Years Back, 10 Years Ahead [chapter]

Gurindar S. Sohi
2001 Lecture Notes in Computer Science  
Acknowledgements The author would like to thank various organizations that have supported his research over the years, including the National Science Foundation (NSF), the Defense Advanced Projects Agency  ...  (DARPA), companies such as Intel and Sun Microsystems, and the University of Wisconsin Graduate School.  ...  Data is read from the data arrays, a speculation is made that it is a cache hit, and the data returned to the processor immediately. Later when the tags are checked, the speculation is verified.  ... 
doi:10.1007/3-540-44577-3_14 fatcat:gvqgv7i6prempcsj4wjldwau5e

An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors [article]

Mohammad Rahmani Fadiheh, Alex Wezel, Johannes Mueller, Joerg Bormann, Sayak Ray, Jason M. Fung, Subhasish Mitra, Dominik Stoffel, Wolfgang Kunz
2021 arXiv   pre-print
Despite recent advances, understanding the intricate implications of microarchitectural design decisions on processor security remains a great challenge and has caused a number of update cycles in the  ...  UPEC scales to a wide range of HW designs, including in-order processors (RocketChip), pipelines with out-of-order writeback (Ariane), and processors with deep out-of-order speculative execution (BOOM)  ...  Through experimental evidence, we show that TESs are possible not only in high-end processors with advanced features, such as out-of-order (OOO) and speculative execution.  ... 
arXiv:2108.01979v2 fatcat:bb2ivpd5irczzexro2yqvm547u

Superscalar out-of-order demystified in four instructions

James C. Hoe
2003 Proceedings of the 2003 workshop on Computer architecture education Held in conjunction with the 30th International Symposium on Computer Architecture - WCAE '03  
Lastly, an exception-triggering instruction tests the support for precise exceptions.  ...  Second, two types of branch instructions, resolving correctly and incorrectly respectively, exercise speculative execution and branch rewind capabilities.  ...  and BEQ) and branch rewinds. • Phase 3: Extend the one-instruction-wide core to also support precise exceptions.  ... 
doi:10.1145/1275521.1275529 dblp:conf/wcae/Hoe03 fatcat:rfgkopr2qjfhbmyzma7kvrbyim

PipeCheck: Specifying and Verifying Microarchitectural Enforcement of Memory Consistency Models

Daniel Lustig, Michael Pellauer, Margaret Martonosi
2014 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture  
We present PipeCheck, a methodology and automated tool for verifying that a particular microarchitecture correctly implements the consistency model required by its architectural specification.  ...  We also specify and analyze the behavior of common microarchitectural optimizations such as speculative load reordering which technically violate formal architecture-level definitions.  ...  MARCO and DARPA.  ... 
doi:10.1109/micro.2014.38 dblp:conf/micro/LustigPM14 fatcat:a5gu36zgsfhipimbsommyuwbn4

Microarchitectural Support for Speculative Register Renaming

Jesus Alastruey, Teresa Monreal, Victor Vinals, Mateo Valero
2007 2007 IEEE International Parallel and Distributed Processing Symposium  
This paper proposes and evaluates a new microarchitecture for out-of-order processors that supports speculative renaming.  ...  Namely, we will use a single Last-Use Predictor that directs both speculative omission and release. We call this mechanism SR-LUP (Speculative Renaming based on Last-Use Prediction).  ...  Acknowledgments This work was supported in part by Diputación General de Aragón grant "Grupo Consolidado de Investigación" (BOA 20/04/2005), Spanish Ministry of Education and Science grant TIN2004-07739  ... 
doi:10.1109/ipdps.2007.370237 dblp:conf/ipps/AlastrueyMVV07 fatcat:hggapxfprbc25aiahtgsjvn6du

Full-system timing-first simulation

Carl J. Mauer, Mark D. Hill, David A. Wood
2002 Proceedings of the 2002 ACM SIGMETRICS international conference on Measurement and modeling of computer systems - SIGMETRICS '02  
This design simplifies software development, leverages existing simulators, and can model microarchitecture timing in detail.  ...  To manage simulator complexity, this paper advocates decoupled simulator organizations that separate functional and performance concerns.  ...  Acknowledgments We thank Craig Zilles for allowing us to use his micro-architectural timing model, Milo Martin for his support integrating the multiprocessor memory timing model, and Ravi Rajwar for describing  ... 
doi:10.1145/511348.511349 fatcat:eyrv6ydcjzetrlkzzhvw4ffwou

Full-system timing-first simulation

Carl J. Mauer, Mark D. Hill, David A. Wood
2002 Proceedings of the 2002 ACM SIGMETRICS international conference on Measurement and modeling of computer systems - SIGMETRICS '02  
This design simplifies software development, leverages existing simulators, and can model microarchitecture timing in detail.  ...  To manage simulator complexity, this paper advocates decoupled simulator organizations that separate functional and performance concerns.  ...  Acknowledgments We thank Craig Zilles for allowing us to use his micro-architectural timing model, Milo Martin for his support integrating the multiprocessor memory timing model, and Ravi Rajwar for describing  ... 
doi:10.1145/511334.511349 dblp:conf/sigmetrics/MauerHW02 fatcat:thhf66fncfcr7f56k264bpym3q

A Systematic Evaluation of Transient Execution Attacks and Defenses [article]

Claudio Canella and Jo Van Bulck and Michael Schwarz and Moritz Lipp and Benjamin von Berg and Philipp Ortner and Frank Piessens and Dmitry Evtyushkin and Daniel Gruss
2019 arXiv   pre-print
Research on transient execution attacks including Spectre and Meltdown showed that exception or branch misprediction events might leave secret-dependent traces in the CPU's microarchitectural state.  ...  Our systematization uncovers 6 (new) transient execution attacks that have been overlooked and not been investigated so far: 2 new exploitable Meltdown effects: Meltdown-PK (Protection Key Bypass) on Intel  ...  1 The initial Meltdown-US disclosure (December 2017) and subsequent paper [56] already made clear that Meltdown-type leakage is not limited to the L1 data cache.  ... 
arXiv:1811.05441v3 fatcat:pbsyzjdmozauvmuoz52ewg26ii

Relational Models of Microarchitectures for Formal Security Analyses [article]

Nicholas Mosier, Hanna Lachnitt, Hamed Nemati, Caroline Trippel
2021 arXiv   pre-print
and the microarchitecture it represents.  ...  First, we demonstrate that our leakage definition faithfully captures a sampling of (transient and non-transient) microarchitectural attacks from the literature.  ...  ACKNOWLEDGEMENTS We would like to thank John Mitchell and Clark Barrett for their valuable discussions and feedback on this work.  ... 
arXiv:2112.10511v1 fatcat:ylcaex3mxfatrl2sezl5hl2iha

Trace table based approach for pipelined microprocessor verification [chapter]

Jun Sawada, Warren A. Hunt
1997 Lecture Notes in Computer Science  
This paper presents several techniques for formally verifying pipellned microprocessor implementations that contain out-of-order execution and dynamic resolution of data-dependent hazards.  ...  This verification was performed incrementally by proving that the specified relations hold for all microarchitectural states reachable from a flushed implementation state, eventually permitting us to prove  ...  Tahar and Kumar [12] verified that their DLX implementation does not have RAW hazards and other pipeline conflicts, but they didn't verify the equivalence between their ISA and micro-architecture.  ... 
doi:10.1007/3-540-63166-6_36 fatcat:lrycriyst5aotf5bgyljirz6ja

FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators

Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Patil, William Reinhart, Darrel Eric Johnson, Jebediah Keefe, Hari Angepat
2007 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)  
It achieves its capabilities by partitioning simulators into a speculative functional model component that simulates the instruction set architecture and a timing model component that predicts performance  ...  Such simulators are useful to virtually all computer system simulator users ranging from architects, through RTL designers and verifiers to software developers.  ...  We expect that FAST simulators, with their combination of speed, accuracy and observability, will provide much insight into the inner workings of computer systems.  ... 
doi:10.1109/micro.2007.36 dblp:conf/micro/ChiouSKPRJKA07 fatcat:76bph2r7bbdfxjwiwwzftrfbyi

FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators

Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Patil, William Reinhart, Darrel Eric Johnson, Jebediah Keefe, Hari Angepat
2007 Microarchitecture (MICRO), Proceedings of the Annual International Symposium on  
It achieves its capabilities by partitioning simulators into a speculative functional model component that simulates the instruction set architecture and a timing model component that predicts performance  ...  Such simulators are useful to virtually all computer system simulator users ranging from architects, through RTL designers and verifiers to software developers.  ...  We expect that FAST simulators, with their combination of speed, accuracy and observability, will provide much insight into the inner workings of computer systems.  ... 
doi:10.1109/micro.2007.4408260 fatcat:z2syt5x7i5fbfh5xnsocklbt6y

Medusa: Microarchitectural Data Leakage via Automated Attack Synthesis

Daniel Moghimi, Moritz Lipp, Berk Sunar, Michael Schwarz
2020 USENIX Security Symposium  
Acknowledgments We would like to thank our reviewers and especially our shepherd, Vasileios Kemerlis, for their suggestions that helped improving the paper.  ...  This work was supported by the European Research Council (ERC) under the European Union's Horizon 2020 research and innovation programme (grant agreement No 681402).  ...  In particular, these exceptions do not block the data flow, and we observe that the pipeline will still speculatively consume the data despite the exception.  ... 
dblp:conf/uss/MoghimiLS020 fatcat:rx3fgpsoo5ch5akhmfqvjvix4e

Characterizing the effects of transient faults on a high-performance processor pipeline

N.J. Wang, J. Quek, T.M. Rafacz, S.J. Patel
2004 International Conference on Dependable Systems and Networks, 2004  
Together, the baseline microarchitectural substrate and software mask more than 9 out of 10 transient faults from affecting correct program execution.  ...  Building upon the failure modes seen in the microarchitecture, fault injections into software were performed to investigate the level of masking that the software layer provides.  ...  We also thank Joel Biskie and Wojciech Magda for their respective contributions. This work was supported by the C2S2 Marco center, NSF grant EIA-0224453, and equipment donation from AMD.  ... 
doi:10.1109/dsn.2004.1311877 dblp:conf/dsn/WangQRP04 fatcat:szmof2m3bzaj5bxwyoupiembki
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