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Verification of Asynchronous Circuits using Timed Automata
2002
Electronical Notes in Theoretical Computer Science
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In this work we apply the timing verification tool OpenKronos, which is based on timed automata, to verify correctness of numerous asynchronous circuits. ...
the STG conventions and that the gate delays are bounded between two given numbers. ...
Ken Stevens, Mike Kishinevski and Luciano Lavagno answered various questions concerning asynchronous circuits. ...
doi:10.1016/s1571-0661(04)80468-7
fatcat:n2k6xfl5cvhl3cr3uyoyx24yde
Automatic synthesis of computation interference constraints for relative timing verification
2009
2009 IEEE International Conference on Computer Design
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The process of creating path-based RT constraints has previously been done by hand with the aid of a formal verification engine. ...
Asynchronous sequential circuit or protocol design requires formal verification to ensure correct behavior under all operating conditions. ...
Relative timing is a method of integrating the verification of timing constraints on an untimed protocol or circuit implementation and converting them into a format that can be used with traditional CAD ...
doi:10.1109/iccd.2009.5413183
dblp:conf/iccd/XuS09
fatcat:gng5cbexyjavhpfowpueonjhhe
Automatic Derivation of Timing Constraints by Failure Analysis
[chapter]
2002
Lecture Notes in Computer Science
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A designated set of delay parameters of a circuit are first set to sufficiently large bounds, and verification runs followed by failure analysis are repeated. ...
Each verification run performs timed state space enumeration under the given delay bounds, and produces a failure trace if it exists. ...
to thank Peter Beerel and Hoshik Kim for helping us to understand their method and giving their latest experimental results, and to thank Bill Coates and Ian Jones for helpful comments to model GasP circuits ...
doi:10.1007/3-540-45657-0_15
fatcat:vedfsd3hbzapbjan3ij6ejcunm
Symbolic verification of timed asynchronous hardware protocols
2013
2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
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A methodology and automated tool flow have been developed for verifying systems of timed asynchronous circuits through compositional model checking of formal models with symbolic methods. ...
Correct interaction of asynchronous protocols requires verification. Timed asynchronous protocols add another layer of complexity to the verification challenge. ...
The performance and power of asynchronous hardware circuits and protocols can be vastly improved with judicious application of timing constraints. ...
doi:10.1109/isvlsi.2013.6654650
dblp:conf/isvlsi/DesaiSO13
fatcat:bd3xxuhzdreqxi4eahq53icctq
Verifying and Testing Asynchronous Circuits Using Lotos
[chapter]
2000
IFIP Advances in Information and Communication Technology
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The approach is illustrated with three case studies that explore speed independence, delay sensitivity and testing of sample asynchronous circuit designs. ...
Tools have been developed for automated verification of conformance and generation of tests. ...
Asynchronous Circuit Verification and Testing
Verifying Asynchronous Circuit Designs The characteristics of asynchronous circuits have implications for verification. ...
doi:10.1007/978-0-387-35533-7_17
fatcat:4jy7uxlrnngz3e2gk7ob6raw3q
Combining CTL, trace theory and timing models
[chapter]
1990
Lecture Notes in Computer Science
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An extension has been implemented that allows the verification of circuits that are not speed-independent, but instead rely on assumptions about the relative delays of their components for correct operation ...
i t t s b u r g h , PA 15213 A b s t r a c t A system that combines CTL model checking and trace theory for verifying speed-independent asynchronous circuits is described. ...
My many discussions with Alain Martin about disciplined methods for designing asynchronous circuits were necessary preparation for designing the fair mutual exclusion circuits in this paper. ...
doi:10.1007/3-540-52148-8_28
fatcat:ahztuveav5fn5l3e3ry23w5qd4
Refinement-based formal verification with heterogeneous timing
2003
International Journal on Software Tools for Technology Transfer (STTT)
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In this case study, we find several race conditions, hazards, and other dangers that were not mentioned in the original publication, and we find additional delay constraints that avoid some of the detected ...
In this paper we propose a refinement-based technique to formally verify data transfer in a heterogeneous timing framework. ...
We thank Mark De Clercq, Mark Greenstreet, Muhua Li, and the anonymous CHARME reviewers for suggestions of improvement of the presented material. ...
doi:10.1007/s10009-002-0096-z
fatcat:m76zf5ngjfevbiexki6xqfcyt4
Advances in Formal Methods for the Design of Analog/Mixed-Signal Systems
2017
Proceedings of the 54th Annual Design Automation Conference 2017 on - DAC '17
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This paper presents an overview of the state-of-the-art in AMS formal verification and asynchronous design that enables the development of analog/asynchronous co-design methods. ...
To cope with the growing complexity of AMS designs, formal methods are required to complement traditional simulation approaches. ...
Acknowledgments This research was supported by EPSRC grant "A4A: Asynchronous design for Analogue electronics" (EP/L025507/1) and National Science Foundation Grant No. CCF-1117515. ...
doi:10.1145/3061639.3072945
dblp:conf/dac/DubikhinMSSY17
fatcat:ujblxhmtvvdsnd3n77lvvriwr4
Verification of Abstracted Instruction Cache of TITAC2: A Case Study
[chapter]
2000
IFIP Advances in Information and Communication Technology
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In this paper, we demonstrate the formal verification of a practical timed asynchronous circuit. ...
The target circuit is obtained by abstracting the instruction cache subsystem of areal asynchronous processor, TITAC 2. We also show several techniques to improve our verification method. ...
It was designed under the scalable-delay-insensitive (SDI) model, where its verification problem can be reduced to that of bounded delay circuits. ...
doi:10.1007/978-0-387-35498-9_33
fatcat:xa5orgjdp5gsviwdn2u7q7g4k4
Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits
2007
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Timed circuits are a class of asynchronous circuits that utilize explicit timing information for optimization throughout the entire design process. ...
Current verification algorithms for timed asynchronous circuits require an explicit state exploration often resulting in state explosion for even modest sized examples. ...
INTRODUCTION Timed circuits are a class of asynchronous circuits that use explicit timing information in circuit synthesis. ...
doi:10.1109/tcad.2006.883912
fatcat:nyff4gjxwrgynais2tm5wlbbgi
Efficient verification of hazard-freedom in gate-level timed asynchronous circuits
2003
ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)
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Timed circuits are a class of asynchronous circuits that utilize explicit timing information for optimization throughout the entire design process. ...
Current verification algorithms for timed asynchronous circuits require an explicit state exploration often resulting in state explosion for even modest sized examples. ...
INTRODUCTION Timed circuits are a class of asynchronous circuits that use explicit timing information in circuit synthesis. ...
doi:10.1109/iccad.2003.159719
fatcat:rnck5zhflzhevnolai4ertplxm
Automatic verification of timed circuits
[chapter]
1994
Lecture Notes in Computer Science
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The formalism, called orbital nets, allows hierarchical verification based on a behavioral semantics of timed trace theory. ...
We present improvements to a geometric timing algorithm that take advantage of concurrency by using partial orders to reduce the time and space requirements of verification. ...
for their discussions and comments during the development of Orbits. ...
doi:10.1007/3-540-58179-0_76
fatcat:zghyi5colbad7kahzmuionxsz4
Relative timing [asynchronous design]
2003
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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Relative timing (RT) is introduced as a method for asynchronous design. Timing requirements of a circuit are made explicit using relative timing. ...
RT synthesis and verification are demonstrated on three example circuits, facilitating transformations from speed-independent circuits to burst-mode and pulse-mode circuits. ...
Burns participated in timing verifications. J. Cortadella and M. Kishinevsky were the first to introduce automatic RT into the CAD tool Petrify. P. Beerel and H. ...
doi:10.1109/tvlsi.2002.801606
fatcat:kblddodo4ferzl763s72becdou
Modular verification of timed circuits using automatic abstraction
2003
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a new approach for verification of timed circuits using automatic abstraction. This approach partitions the design into modules, each with constrained complexity. ...
This approach converts a verification problem with big exponential complexity to a set of sub-problems, each with small exponential complexity. ...
ACKNOWLEDGMENTS We would like to thank Wendy Belluomini of IBM and Tomohiro Yoneda of the Tokyo Institute of Technology for their helpful comments. ...
doi:10.1109/tcad.2003.816214
fatcat:wckiciqqjzew5khdxlixd47haa
Asynchronous design methodologies: an overview
1995
Proceedings of the IEEE
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These include Huffman asynchronous circuits, burst-mode circuits, micropipelines, template-based and trace theory-based delay-insensitive circuits, signal transition graphs, change diagrams, and compilation-based ...
Asynchronous circuits generally require extra time due to their signaling policies, thus increasing average-case delay. ...
Acknowledgments This paper has been greatly improved by a number of patient readers, including Gaetano Borriello, John Brzozowski, Al Davis, David Dill, Carl Ebeling, Jo Ebergen, Henrik Hulgaard, Carl ...
doi:10.1109/5.362752
fatcat:2wtrcnhd3beeve2vzcuij6vydq
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