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IFIP Advances in Information and Communication Technology
The target circuit is obtained by abstracting the instruction cache subsystem of areal asynchronous processor, TITAC 2. We also show several techniques to improve our verification method. ... In this paper, we demonstrate the formal verification of a practical timed asynchronous circuit. ... That is, in this case study, we verify the following property of the instruction cache subsystem: The LSB of the instruction read from the cache subsystem is the one stored in the location of the main ...doi:10.1007/978-0-387-35498-9_33 fatcat:xa5orgjdp5gsviwdn2u7q7g4k4