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Call for Papers
2009
IEICE ESS FUNDAMENTALS REVIEW
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PCB routing, etc ...
[5] High-Level/Behavioral/Logic Synthesis and Optimization: High-Level/behavioral/RTL synthesis, technology-independent optimization, technology mapping, interaction between logic design and layout, ...
Dallas is known for living large and thinking big. ...
doi:10.1587/essfr.3.1_82
fatcat:2nsryqdt6zhv3oztnpzt3ua54m
Call for Papers
2010
IEICE ESS FUNDAMENTALS REVIEW
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package/PCB routing, etc. [8] Timing, Power, Thermal Analysis and Optimization: Deterministic and statistical static timing analysis, statistical performance analysis and optimization, low power design ...
[12] Analog, RF and Mixed Signal Design and CAD:
Analog/RF synthesis, analog layout, verification and
simulation techniques, noise analysis, mixed-signal
design considerations. ...
Tutorial and special session authors are referred to the ICASSP website for additional information regarding submissions.
IMPORTANT DEADLINES ...
doi:10.1587/essfr.4.87
fatcat:msi3y3dv4vcvlf6xzhxb3yrmra
The Electrical Characteristics Investigation of the Module-Level Miniaturization with Embedded Device Technology
2009
Transactions of The Japan Institute of Electronics Packaging
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In addition, the CPUembedded SiP has sufficient signal transmission properties for a data rate of 4 Gbps. ...
Previously, we developed a high-density assembly technology to miniaturize the motion control CPU SiP for humanoid robots. ...
small: 12.6 psec for the all-B 2 it PCB and 13.8 psec for the combination PCB, respectively. ...
doi:10.5104/jiepeng.2.139
fatcat:w7jjalgzpna2boiu7egd2rd7b4
Development of an electronic vehicular traffic signal controller
2006
Journal of Science and Technology (Ghana)
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Finite state machine concept was used in the design of the signal controller and the implementation carried out using Large Scale Integrated (LSI) devices. ...
The controller is driven by a real-time clock and can be configured for a six-phase intersection. ...
ACKNOWLEDGEMENTS The author would like to thank the following for their invaluable suggestions and assistance: Professor E.A Jackson and staff (academic and technical) of the Department of Electrical and ...
doi:10.4314/just.v26i1.32969
fatcat:5dcfxclccbaqfk2xkh2sihkq6i
Reduction of common-mode excitation on a differential transmission line bend by imbalance control
2014
IEICE Communications Express
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Herein two methods are proposed to improve the symmetry and reduce the commonmode at the line bend on a printed circuit board. ...
However, in an actual PCB, it is almost impossible to design a completely symmetric transmission line because a transmission line should have bends to connect the driver LSI and receiver LSI, which may ...
In order to avoid common-mode generation, a differential transmission line on a printed circuit board (PCB) should have symmetric layout. ...
doi:10.1587/comex.3.295
fatcat:eisyuniedna5dfsaaerkyrinpu
Evolution of CAD tools towards third generation custom VLSI design
1987
Revue de Physique Appliquée
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Abstract. 2014 In this paper trends in CAD for application specific IC's (ASIC) are discussed. Shortage of skilled silicon ...
Un programme symbolique et interprétatif doit supporter la génération du « layout » ainsi que le test et la simulation temporelle. ...
In particular however they are the results of a joint view within the IMEC research group and of the partners in the Esprit 97 and the MR03KUL EEC microelectronics project. ...
doi:10.1051/rphysap:0198700220103100
fatcat:ni4fa4k25jfjli7r7gnmf5zhdm
An Inductive-Coupling Inter-Chip Link for High-Performance and Low-Power 3D System Integration
[chapter]
2010
Solid State Circuits Technologies
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Acknowledgements This work has been in part supported by the Grant-in-Aid for JSPS fellows and the Central Research Laboratory of Hitachi Limited. ...
In 3D system integration, we can implement analog and digital circuits in LSI chips in their optimal process and they are stacked and connected through vertical inter-chip link. ...
Total layout area for the inductive coupling link is 2.82mm 2 . Aggregated bandwidth is 19.2Gb/s. ...
doi:10.5772/6885
fatcat:v3qdnxph5fap7mi4mslout7m6y
New products
1982
Computer
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The PCB layout module supports interactive layout or digitizing of multilayer boards up to 32" x 32" with one mil resolution. ...
as a complete package or as individual modules: a general drawing core, a schematic drawing module, or a PCB layout module. ...
doi:10.1109/mc.1982.1653976
fatcat:yqmyosy375emdekgmfpdjuzh4y
LHCb base-line level-0 trigger 3D-Flow implementation
1999
Nuclear Instruments and Methods in Physics Research Section A : Accelerators, Spectrometers, Detectors and Associated Equipment
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Details are also given on timing and synchronization issues, ASIC (Application Specific Integrated Circuit) design verification, real time performance monitoring and design (software and hardware) development ...
Full implementation of a 3D-Flow system, for the most complex trigger algorithm, requires 320 cables to North and South crates and 40 cables to East and West crates (cable cost = $2 each). ...
Fathi from National Semiconductors for information regarding LVDS, and J. Naples for editing assistance. ...
doi:10.1016/s0168-9002(99)00496-9
fatcat:agk22vezdfcovnl4hcwao6lply
ARCADE — An architecture for CAD in electronics
1984
Computers in industry (Print)
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[12] for LSI layout, -in test preparation work LASAR for test pattern generation. ...
A part can be a PCB, an LSI, a connector, a transducer etc., and all these parts belong to the same (sub-)assembly. ...
doi:10.1016/0166-3615(84)90033-2
fatcat:et5cpwrffvenbl2r6cf7xstf3u
A chip prototyping substrate
2005
SIGARCH Computer Architecture News
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FAST combines configurable and fixedfunction hardware and software to facilitate rapid prototyping by utilizing components optimized for their particular tasks: FPGAs for interconnect and glue logic; processors ...
for rapid program execution; and SRAMs for fast memory. ...
Acknowledgements We would like to thank Alan Swithenbank and Wade Gupta for their contribution to the FAST PCB layout and fabrication. ...
doi:10.1145/1105734.1105740
fatcat:jsvwufawqfgpfpyvuhsxr7qubi
Improving Laser Speckle Imaging Technology
2022
Zenodo
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I work at the Institute for Computer Science and Control (SZTAKI), where my research group recently started to explore the field of laser speckle imaging with a focus on improving Laser Speckle Contrast ...
In my MSc thesis I introduce the literature and related works of laser speckle imaging outlining the underlying physics and the mathematics behind. ...
In the medical field, LSI can be used for the flowmetry of microcirculation and blood perfusion. ...
doi:10.5281/zenodo.6340677
fatcat:vfxt5gcg4zgunlgdfpihqrhqvi
A historical review of circuit simulation
1984
IEEE Transactions on Circuits and Systems
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(one of the first) for the electrical and physical design and verification of an integrated circuit design methodology. ...
The interested reader is referred to an excellent review article on layout by Soukup [70] . In a recent paper, Newton has examined the broad range of layout problems for VLSI circuits [54] . II. ...
doi:10.1109/tcs.1984.1085422
fatcat:4mfobrxqobgcnlsnd37vq3qegy
Introducing core-based system design
1997
IEEE Design & Test of Computers
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Acknowledgments The National Science Foundation Career Award MIP 95-01615, NSF/DARPA grant ASC-96-34947, and NSF grant EEC 89-43166 supported this work. ...
Unlike soft and firm cores that depend on specific EDA tools and data formats for system integration, hard cores include layout and timing information. ...
These are compatible with internal core test methods and optimized for area and
System-level integration and test True, there is no inherent reason for this skimping to change as the design size moves ...
doi:10.1109/54.632877
fatcat:zncsmyx5qzd3tmnbkuxnapz5hm
A 4.8-6.4-Gb/s serial link for backplane applications using decision feedback equalization
2005
IEEE Journal of Solid-State Circuits
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The transmitter features a programmable two-tap feed forward equalizer and the receiver uses an adaptive four-tap decision feedback equalization to compensate for the losses in the channel at 6.4 Gbps. ...
Vishnu Balan (S'95-M'96) received the B.S. degree in electronics and communications engineering from the Indian Institute of Technology, Madras, in 1995 and the M.S. degree in electrical engineering from ...
It consists of a data rotator which aligns data for optimal timing at the serializer, two 4:1 serializers (one each for data and 1T delayed data), predriver, and a CML 50-driver. ...
doi:10.1109/jssc.2005.848180
fatcat:72pzz5yhenadhl5orbau3arut4
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