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Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode

Davide Rossi, Francesco Conti, Manuel Eggimann, Alfio Di Mauro, Giuseppe Tagliavini, Stefan Mach, Marco Guermandi, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini
<span title="">2021</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/cz5rf4o3ezafnl4kjpq643g32e" style="color: black;">IEEE Journal of Solid-State Circuits</a> </i> &nbsp;
We present Vega, an IoT end-node SoC capable of scaling from a 1.7 μW fully retentive cognitive sleep mode up to 32.2 GOPS (@ 49.4 mW) peak performance on NSAAs, including mobile DNN inference, exploiting  ...  1.6 MB of state-retentive SRAM, and 4 MB of non-volatile MRAM.  ...  CONCLUSION We presented Vega, an always-on IoT end-node SoC featuring a 1.7 µW fully retentive cognitive wake-up unit coupled with a power/performance/precision scalable SoC.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/jssc.2021.3114881">doi:10.1109/jssc.2021.3114881</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/mnu3j7pw2ffhbhbjhnqnqutogq">fatcat:mnu3j7pw2ffhbhbjhnqnqutogq</a> </span>
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