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Embedded software-based self-test for programmable core-based designs

A. Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, L. Chen, S. Dey
2002 IEEE Design & Test of Computers  
A core-based SoC incorporates multiple complex, heterogeneous components on a single piece of silicon; these can include digital, analog, mixed-signal, RF, micromechanical, and other kinds of systems.  ...  Because digital logic testers cannot do precise analog testing, externally testing mixed-Embedded Software-Based Self-Test for Programmable Core-Based Designs Embedded Systems 18 The programmable cores  ...  We have applied this test synthesis program to Parwan and DLX processors.  ... 
doi:10.1109/mdt.2002.1018130 fatcat:fyyiaiaoj5dvzf6otfkzjqx25m

Prospects for using soft processors in systems-on-a-chip based on field-programmable gate arrays

I. E. Tarasov, D. S. Potekhin, O. V. Platonova
2022 Российский технологический журнал  
The control of digital signal processing hardware as part of an SoC is the promising application area for soft processors.  ...  For soft processors, a unified design route based on selecting architectural parameters qualitatively corresponding to control tasks was considered.  ...  In addition, since static memory blocks may be also used by hardware accelerators, memory saved for storing programs may be significant when selecting the processor architecture.  ... 
doi:10.32362/2500-316x-2022-10-3-24-33 fatcat:vd57jn2xmffblbthhgkaecai7i

EP32 - a 32-bit Foth Micorprocessor

Edvin Hjrtland, Li Chen
2007 2007 Canadian Conference on Electrical and Computer Engineering  
It is a stack based processor, well suited for the Forth programming language. The instruction set includes 35 RISC-like instructions.  ...  The processor will be synthesized with a radiation-hard-by-design digital library in the future for space applications.  ...  ACKNOWLEDGMENT The authors would like to thank Umesh Patel with Goddard Space Flight Center, NASA for providing the original design of the EP32 and the technical support for this project.  ... 
doi:10.1109/ccece.2007.135 fatcat:yjxfnwuftffmrj7hqifmci4bbq

Using rapid prototyping in computer architecture design laboratories

James O. Hamblen, Henry Owen, Sudhakar Yalamanchili, Binh Dao
1996 Proceedings of the 1996 workshop on Computer architecture education - WCAE-2 '96  
A core sequence of six required courses for computer engineering students has been developed.  ...  Changes are limited to the bit vector array size declarations for variables and signals in the data path. The smaller model requires machine language test programs that use 8-bit integer values.  ...  The outputs of this VHDL module are the various control signals used in the processor. The synthesis tool automatically performs logic minimization and multi-level logic synthesis.  ... 
doi:10.1145/1275152.1275156 dblp:conf/wcae/HamblenOYD96 fatcat:wyfxm6bzxbbl7b2bgbw2oh7mtu

Synthesis of pipelined DSP accelerators with dynamic scheduling

Patrick Schaumont, Bart Vanthournout, Ivo Bolsens, Hugo De Man
1995 Proceedings of the 8th international symposium on System synthesis - ISSS '95  
In this paper, a methodology is presented to synthesize high throughput DSP functions into accelerator processors containing a datapath of highly pipelined, bit-parallel hardware units.  ...  Vernalde from IMEC for the constructive remarks during the writing of this paper. The work is also founded on the netlist optimization tools developed by L. Rijnders and Z.  ...  In this context, he introduced functional programming, using Lisp, and object oriented programming, using Smalltalk.  ... 
doi:10.1145/224486.224503 dblp:conf/isss/SchaumontVBM95 fatcat:tddaixxn5fbidboovjlcdjsboy

Embedded software-based self-testing for SoC design

A. Krstic, W. C. Lai, K. T. Cheng, L. Chen, S. Dey
2002 Proceedings - Design Automation Conference  
In this methodology, the programmable cores are used for on-chip test generation, measurement, response analysis and even diagnosis.  ...  After the programmable core on a System-on-Chip (SoC) has been self-tested, it can be reused for testing on-chip buses, interfaces and other non-programmable cores.  ...  Mak, Intel on many stimulating discussions and useful insights on the topics in this paper.  ... 
doi:10.1145/513918.514010 dblp:conf/dac/KrsticLCCD02 fatcat:wanljgmetzfb7pncwaxcsm3x5e

Embedded software-based self-testing for SoC design

A. Krstic, W. C. Lai, K. T. Cheng, L. Chen, S. Dey
2002 Proceedings - Design Automation Conference  
In this methodology, the programmable cores are used for on-chip test generation, measurement, response analysis and even diagnosis.  ...  After the programmable core on a System-on-Chip (SoC) has been self-tested, it can be reused for testing on-chip buses, interfaces and other non-programmable cores.  ...  Mak, Intel on many stimulating discussions and useful insights on the topics in this paper.  ... 
doi:10.1145/514009.514010 fatcat:2nluc3xsorg2zegsuuliffxv7i

Simulation and Verification of Self Test 16Bit Processor

Manoranjan Pradhan
2011 International Journal of Computer Applications  
The design entry, synthesis, and simulation of processor are done by using Xilinx ISE 10.1 software and implemented on XC2S200-6pq208 Spartan-II FPGA device.  ...  The control unit generates all the control signals needed to control the coordination among the entire component of the processor.  ...  The synthesis results and simulation results of processor are presented for justification.  ... 
doi:10.5120/2394-3180 fatcat:bdhebxpeabb2rai5ni2rmp6yxe

Design and Simulation of an 8-bit Dedicated Processor for calculating the Sine and Cosine of an Angle using the CORDIC Algorithm [article]

Aman Chadha, Divya Jyoti, M. G. Bhatia
2011 arXiv   pre-print
This paper describes the design and simulation of an 8-bit dedicated processor for calculating the Sine and Cosine of an Angle using CORDIC Algorithm (COordinate Rotation DIgital Computer), a simple and  ...  We have proposed a dedicated processor system, modeled by writing appropriate programs in VHDL, for calculating the Sine and Cosine of an angle.  ...  Instructions for performing a task are hardwired into the processor itself, i.e., the program is built right into the microprocessor circuit itself [2] .  ... 
arXiv:1111.1086v1 fatcat:uy3agacocramnpxpvm2nxyunmy

Low power IEEE 802.15.4a UWB digital Rx baseband architecture

Michael De Nil, Ben Busze, Alex Young, Dries Neirynck, Hans Pflug, Kathleen Philips, Jos Huisken, Jan Stuyt, Harmke de Groot
2010 2010 IEEE International Conference on Ultra-Wideband  
The architecture consists of a programmable application specific instruction set processor and a set of application specific integrated circuits.  ...  This paper presents a low power ultra-wide band digital receiver baseband architecture for handling IEEE 802.15.4a packets in real-time.  ...  For synthesis Synplify Pro was used, place and route was performed with Xilinx ISE.  ... 
doi:10.1109/icuwb.2010.5614622 fatcat:cuqbciijrzci7n2ju7u4v4z2qm

From Boolean algebra to processor architecture and assembly programming in one semester

Jose Silva Matos, Jose Carlos Alves, Helio Sousa Mendonca, Antonio Jose Araujo
2014 Design of Circuits and Integrated Systems  
At the same time its coverage was extended to include low-level processor architecture issues, and to teach assembly programming for the MIPS processor.  ...  Digital Systems Laboratory is an introductory course on digital design, with the classical task of teaching Boolean algebra and combinational and sequential circuit design, using gates, flip-flops and  ...  an introduction to modern digital system design using hardware description languages and tools for specification, simulation and synthesis, and iii) to introduce the fundamental concepts associated with  ... 
doi:10.1109/dcis.2014.7035605 fatcat:drpcdw6ovjfkvcrgabhqjqoplm

The application of threshold logic to the design of sequential machines

Gilbert M. Masters, Richard L. Mattson
1966 Annual Symposium on Switching and Automata Theory  
slowly fading channel, diversity techniques for fading multi-path channels, Digital signal over a frequency-selective, slowly fading channel, coded wave forms for fading channels, multiple antenna systems  ...  Digital Communication through fading multi-path channels: Characterization of fading multi-path channels, the effect of signal characteristics on the choice of a channel model, frequency-Nonselective,  ...  Processor and memory organization: Structural unit in as processor, processor selection for an embedded systems.  ... 
doi:10.1109/swat.1966.29 dblp:conf/focs/MastersM66 fatcat:ierxfghv4vcpbbh2iaktwfdzlm

A highly parameterizable parallel processor array architecture

Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jurgen Teich
2006 2006 IEEE International Conference on Field Programmable Technology  
In this paper a new class of highly parameterizable coarse-grained reconfigurable architectures called weakly programmable processor arrays is discussed.  ...  The instruction set of a WPPE is also kept small and specific to instructions commonly needed in digital signal processing.  ...  The assumption for a program to consist only of four VLIW instructions is realistic, since different digital filter algorithms, like for example edge detection, can already be implemented with programs  ... 
doi:10.1109/fpt.2006.270293 dblp:conf/fpt/KisslerHKT06 fatcat:k6woefmcnjcypjc6h4t2p6fqju

Software synthesis and code generation for signal processing systems

S.S. Bhartacharyya, R. Leupers, P. Marwedel
2000 IEEE transactions on circuits and systems - 2, Analog and digital signal processing  
optimization techniques; and the compilation of C programs into streamlined machine code for programmable DSP processors using architecture-specific and retargetable back-end optimizations.  ...  The role of software is becoming increasingly important in the implementation of digital signal processing (DSP) applications.  ...  At the system-specification level, the past several years have seen increased use of block-diagram-based graphical programming environments for digital signal processing.  ... 
doi:10.1109/82.868454 fatcat:4udasl3dqnekthi5ymwgttnuti

Implementation of a reconfigurable ASIP for high throughput low power DFT/DCT/FIR engine

Hanan M Hassan, Karim Mohammed, Ahmed F Shalash
2012 EURASIP Journal on Embedded Systems  
Programming of the processor is done through a mid-level language that combines register-specific instructions with DFT/DCT/FIR specificinstructions.  ...  The engine is intended for use in an accelerator-chain implementation of wireless communication systems.  ...  Authors of [1] [2] [3] used Digital Signal Processors (DSPs) owing to their high configurability and adaptive capabilities.  ... 
doi:10.1186/1687-3963-2012-3 fatcat:pruqbuv2frceta7i6jlkghb3ma
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