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Vector class on limited local memory (LLM) multi-core processors
2011
Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems - CASES '11
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Limited Local Memory (LLM) multi-core architecture is a promising solution for scalable memory hierarchy. ...
In this paper, we propose and implement a scheme to manage vector class in the local memory present in each core of LLM multi-core architecture. ...
CONCLUSION AND FUTURE WORK In this paper, we propose a vector class with data management on Limited Local Memory (LLM) multi-core architecture. ...
doi:10.1145/2038698.2038731
dblp:conf/cases/BaiLS11
fatcat:4n3lcjbzwfgixijuuvwf4pypom
Monitoring Integrity Using Limited Local Memory
2013
IEEE Transactions on Information Forensics and Security
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In this paper, we present a new machine architecture called limited local memory (LLM), which we leverage to set up an alternative tamper-proof execution environment for system integrity monitors. ...
This architecture leverages recent trends in multicore chip design to equip each processing core with access to a small, private memory area. ...
LLM extends a standard multi-core machine by adding local memory to each core. ...
doi:10.1109/tifs.2013.2266095
fatcat:6rz6ootmnzelvp4sk73uzyptsy
VPC: Scalable, Low Downtime Checkpointing for Virtual Clusters
2012
2012 IEEE 24th International Symposium on Computer Architecture and High Performance Computing
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A virtual cluster (VC) consists of multiple virtual machines (VMs) running on different physical hosts, interconnected by a virtual network. ...
Additionally, VPC incurs a memory overhead of no more than 9%. In all cases, VPC's performance overhead is less than 16%. ...
Each server has 24 AMD Opteron 6168 processors (1.86GHz), and each processor has 12 cores. The total assigned RAM for each server is 11GB. ...
doi:10.1109/sbac-pad.2012.31
dblp:conf/sbac-pad/LuRK12
fatcat:4axv6vqxqre2zp2a4wlpajhyea
Reconstructing Hardware Transactional Memory for Workload Optimized Systems
[chapter]
2011
Lecture Notes in Computer Science
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This creates grand challenges to architectural and system designs, as well as to methods of programming these systems, which form the core theme of APPT 2011. ...
With the continuity of Moore's law in the multicore era and the emerging cloud computing, parallelism has been pervasively available almost everywhere, from traditional processor pipelines to large-scale ...
The first alternative is called the limited local memory(LLM). Local memory in the CELL BE processor is a typical representative [2] of this architecture. ...
doi:10.1007/978-3-642-24151-2_1
fatcat:32cx745cn5cfdm5sbeah6eyiey
Specialization of the Cell SPE for Media Applications
2009
2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors
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There is a clear trend towards multi-cores to meet the performance requirements of emerging and future applications. ...
A different way to scale performance is, however, to specialize the cores for specific application domains. ...
Moreover, the system provides local memory with a DMA unit. The cores itself though are very simple and do not have any real specialization. ...
doi:10.1109/asap.2009.10
dblp:conf/asap/MeenderinckJ09
fatcat:zyhcxcaomvcczchn3zi44cljzi
A Tale of Three Runtimes
[article]
2014
arXiv
pre-print
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We developed a hierarchical mapping solution using auto-parallelizing compiler technology to target three different runtimes relying on event-driven tasks (EDTs). ...
Lastly, our templated expression based multi-dimensional spaces can be extended to decompose recursively and adapt at runtime, which will be the subject of future work. ...
Our solution uses auto-parallelizing compiler technology to target three different runtimes relying on event-driven tasks (EDTs) via a runtime-agnostic C++ layer, which we have retargeted to Intel's Concurrent ...
arXiv:1409.1914v1
fatcat:zkxw27apr5fcxclosm7hvsp5vm
tgp: AnRPackage for Bayesian Nonstationary, Semiparametric Nonlinear Regression and Design by Treed Gaussian Process Models
2007
Journal of Statistical Software
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Likewise, there is also an argument (slice) which allows one to specify which slice of the posterior predictive data is desired. ...
The tgp package for R is a tool for fully Bayesian nonstationary, semiparametric nonlinear regression and design by treed Gaussian processes with jumps to the limiting linear model. ...
locally. ...
doi:10.18637/jss.v019.i09
fatcat:jrtof4cusbfc3jtsyiea75qnuq
Ensuring System Integrity Using Limited Local Memory
2011
Preserved Fulltext
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In this paper, we present a new machine architecture called limited local memory (LLM), which we leverage to set up an alternative tamper-proof execution environment for system integrity monitors. ...
This architecture leverages recent trends in multicore chip design to equip each processing core with access to a small, private memory area. ...
LLM extends a typical multi-core machine by adding a privileged processing core (core0). Core0 has exclusive access to a small private memory area (hence the name "limited local memory"). ...
doi:10.7282/t36113v4
fatcat:6lgjn6gtxvgntdzvqo4iq2vfcy
Mobile Match-on-Card Authentication Using Offline-Simplified Models with Gait and Face Biometrics
2018
IEEE Transactions on Mobile Computing
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This further requires attackers to monitor the device memory/processor to obtain biometric information, but still works without interaction of the legitimate user. ...
− v 2 | (3) We refer to feature distance vectors originated by the same person as being of the positive class P and to those originated by different people as being of the negative class N . ...
doi:10.1109/tmc.2018.2812883
fatcat:ymsyjs5lwzerdb6ybdp4rfbxfq
Trends in distributed and cooperative database management
[chapter]
1990
Lecture Notes in Computer Science
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llm mN mN ,/ : ¢ t Figure 3 .4: Data Exchange on SQL Command Level at check-in time. ...
Obviously, data exchange with a local workstation DBMS in single-user mode can be much faster than with a remote DBMS in a multi-user environment. ...
doi:10.1007/3-540-53397-4_40
fatcat:4g4a6sjcyrez7fhfkb2kjff2v4
Service-oriented sensor–actuator networks: Promises, challenges, and the road ahead
2007
Computer Communications
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We investigate the benefits of SOSANETs in the context of TinySOA, a prototype SOSANET that we developed on top of TinyOS. ...
In this paper, we first discuss some of the limitations of current SANET architectures. ...
To illustrate multi-query optimization in TinySOA, we discuss the example of multi-event detection. Event detection is a major function of a SANET's query processor. ...
doi:10.1016/j.comcom.2007.05.036
fatcat:xk4i3jwc4nhx5jg64rxymxeqza
Graph Neural Networks in Particle Physics: Implementations, Innovations, and Challenges
[article]
2022
arXiv
pre-print
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With the wide-spread adoption of GNNs in industry, the HEP community is well-placed to benefit from rapid improvements in GNN latency and memory usage. ...
In particular, graph neural networks (GNNs) are an impactful class of GDL algorithms that operate on graphs. ...
We outline the core challenges in applying GNNs in particle physics below. ...
arXiv:2203.12852v2
fatcat:ohq4r53korhpbgy3yvl3q7tyay
Incrementally Learning Objects by Touch: Online Discriminative and Generative Models for Tactile-Based Recognition
2014
IEEE Transactions on Haptics
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We present experimental results for both supervised and unsupervised learning tasks using the iCub humanoid, with tactile sensors on its five-fingered anthropomorphic hand, and 10 different object classes ...
We also describe incremental unsupervised learning mechanisms, based on novelty scores and extreme value theory, when teacher labels are not available. ...
For example, Schöpfer, Ritter and Heidemann [6] used a local linear map (LLM) neural network trained on features 1 obtained using a low-cost 16 ⇥ 16 tactile sensor array mounted on a Unimation 6-DOF ...
doi:10.1109/toh.2014.2326159
pmid:25532151
fatcat:ljc4r4eu6rfcjip7m5bqzu3tfm
Pencil Code
[article]
2020
Zenodo
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Sisu: Cray XC30 with 1472 2.6 GHz Intel (Xeon) Sandy Bridge 8 core (E5-2670) processors (11, 776 cores in total), 2 GB of memory per core. ...
Hermit: Cray XE6 with 7104 2.3 GHz AMD Interlagos 16 core processors (113,664 cores in total), nodes with either 1 or 2 GB of memory per core. ...
. . . . . . . . . . . . . . . . . 112 lfirstpoint . . . . . . . . . . . . . . . . . . . . 112 lhcond global . . . . . . . . . . . . . . . . . 190 lignore Bext in b2 . . . . . . . . . . . . . . 190 LLm ...
doi:10.5281/zenodo.3961647
fatcat:wrpaz23op5a2doysqq3zk7xme4
The Pencil Code, a modular MPI code for partial differential equations and particles: multipurpose and multiuser-maintained
[article]
2021
Zenodo
Preserved Fulltext
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Sisu: Cray XC30 with 1472 2.6 GHz Intel (Xeon) Sandy Bridge 8 core (E5-2670) processors (11, 776 cores in total), 2 GB of memory per core. ...
Hermit: Cray XE6 with 7104 2.3 GHz AMD Interlagos 16 core processors (113,664 cores in total), nodes with either 1 or 2 GB of memory per core. ...
doi:10.5281/zenodo.4553325
fatcat:2icmms6n3zawfmoceifloeo6me
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