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Variations-aware low-power design with voltage scaling

Navid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm
2005 Proceedings of the 42nd annual conference on Design automation - DAC '05  
We present a new methodology which takes into consideration the effect of Within-Die (WID) process variations on a low-voltage parallel system.  ...  We show that in the presence of process variations one should use a higher supply voltage than would otherwise be predicted to minimize the power consumption of a parallel systems.  ...  In this paper we present a new methodology for low-power design which takes into consideration the effect of WID process variations in the design of a parallel system.  ... 
doi:10.1145/1065579.1065717 dblp:conf/dac/AziziKDN05 fatcat:k7x67clxgvfednlcm7m6jbnbya

Variations-aware low-power design with voltage scaling

N. Azizi, M.M. Khellah, V. De, F.N. Najm
2005 Proceedings. 42nd Design Automation Conference, 2005.  
We present a new methodology which takes into consideration the effect of Within-Die (WID) process variations on a low-voltage parallel system.  ...  We show that in the presence of process variations one should use a higher supply voltage than would otherwise be predicted to minimize the power consumption of a parallel systems.  ...  In this paper we present a new methodology for low-power design which takes into consideration the effect of WID process variations in the design of a parallel system.  ... 
doi:10.1109/dac.2005.193866 fatcat:lplbaanjtjf3pfxudl7gttnkym

Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling

N. Azizi, M.M. Khellah, V.K. De, F.N. Najm
2007 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
scales.  ...  We present a new methodology which takes into consideration the effect of within-die (WID) process variations on a low-voltage parallel system.  ...  Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling Abstract-We present a new methodology which takes into consideration the effect of within-die (WID) process variations on a low-voltage  ... 
doi:10.1109/tvlsi.2007.899226 fatcat:sdvwb7x6uvffjkj22lwy5kn4qe

Variation-and-aging aware low power embedded SRAM for multimedia applications

Na Gong, Shixiong Jiang, Anoosha Challapalli, Manpinder Panesar, Ramalingam Sridhar
2012 2012 IEEE International SOC Conference  
Considering both of the process variation and aging effect, the proposed design adopts an optimal high voltage for spatial voltage scaling to achieve high power efficiency.  ...  This paper presents a low power embedded SRAM memory design for MPEG-4 video processors.  ...  Variation-Aging aware Low Power SRAM Design To achieve higher power savings, we propose a novel memory design based on SVS: the higher n HOBs are stored in cells with high V dd (Vdd_Hi) to enhance its  ... 
doi:10.1109/socc.2012.6398371 dblp:conf/socc/GongJCPS12 fatcat:prhx2pmvqnefxmol3iqfoiu2xq

Enhancing the Efficiency of Energy-Constrained DVFS Designs

Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori
2013 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Index Terms-Context-aware design, dynamic voltage and frequency scaling, lifetime energy reduction, low-power design.  ...  Dynamic voltage and frequency scaling (DVFS) is a popular energy reduction technique that allows a hardware design to reduce average power consumption while still enabling the design to meet a high-performance  ...  For designs with low R hi , where leakage power variations impact total power more significantly, we see that variations impact average power savings by less than 2%. E.  ... 
doi:10.1109/tvlsi.2012.2219084 fatcat:oziivetnvnfftkbfyukbri5ck4

Coping with Variations through System-Level Design

Nilanjan Banerjee, Saumya Chandra, Swaroop Ghosh, Sujit Dey, Anand Raghunathan, Kaushik Roy
2009 2009 22nd International Conference on VLSI Design  
by trading off quality of the result, variation-aware system-level power analysis, and system-level power management under variations.  ...  As the magnitude of parameter variations increases with technology scaling, these techniques are not sufficient to address the negative impact that variations have on IC performance, power, yield, and  ...  Overview We propose design-specific and chip-specific approaches to designing variation-aware power management schemes.  ... 
doi:10.1109/vlsi.design.2009.96 dblp:conf/vlsid/BanerjeeCGDRR09 fatcat:zccl2syeavdgjfrlpxjgk7cuue

Containing the Nanometer "Pandora-Box": Cross-Layer Design Techniques for Variation Aware Low Power Systems

Georgios Karakonstantis, Abhijit Chatterjee, Kaushik Roy
2011 IEEE Journal on Emerging and Selected Topics in Circuits and Systems  
This paper presents an overview of techniques at various levels of design abstraction that lead to low power and variation aware logic, memory and mixed-signal circuits and can potentially assist in meeting  ...  The contradictory design requirements for low-power and system robustness, is one of the most challenging design problems of today.  ...  CONCLUSION An overview of several techniques for the design of variation aware and low power systems was conducted.  ... 
doi:10.1109/jetcas.2011.2135590 fatcat:3tnl6lww3jesfmv5ptqgpv45le

VaMV: Variability-aware Memory Virtualization

L. A. D. Bathen, N. D. Dutt, A. Nicolau, P. Gupta
2012 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)  
1) SRAM voltage scaling, 2) DRAM power variability, and 3) Efficient dynamic policydriven variability-aware memory allocation.  ...  resources according to their characteristics (e.g., power consumption), and selectively maps data to the best-fitting memory resource (e.g., high-utilization data to low-power memory space).  ...  TABLE I I MEMORY RANKING Rank Description R1 Voltage Scaled SRAM: process variations, low power, & increased access latency R2 Nominal Vdd On-Chip Memories: higher power consumption R3 Low-power  ... 
doi:10.1109/date.2012.6176479 dblp:conf/date/BathenDNG12 fatcat:icvxfc7gffeknca4byw6pewe5q

Parametric yield driven resource binding in behavioral synthesis with multi-Vth/Vdd library

Yibo Chen, Yuan Xie, Yu Wang, Andres Takach
2010 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)  
for low power.  ...  Experimental results show that significant power reduction can be achieved with the proposed variation-aware framework, compared with traditional worst-case based deterministic approaches.  ...  Nevertheless, variation-aware low power exploration for behavioral synthesis is still in its infancy.  ... 
doi:10.1109/aspdac.2010.5419783 dblp:conf/aspdac/ChenXWT10a fatcat:yw3oraydfvdx3i5k36c2czjomq

Variability-aware memory management for nanoscale computing

N. Dutt, P. Gupta, A. Nicolau, L. A. D. Bathen, M. Gottscho
2013 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)  
As a result, it is imperative for designers to build variation-aware software stacks that may adapt and opportunistically exploit said variations to increase system performance/responsiveness as well as  ...  to the effects of variations (e.g., power).  ...  Data, low-power/irregular access Sample Fig. 7 . 7 SPM alloca7on (no voltage scaling), tradi7onal malloc, tradi7onal context switching M1: Voltage scale on--chip memory, variability aware off--chip memory  ... 
doi:10.1109/aspdac.2013.6509584 dblp:conf/aspdac/DuttGNBG13 fatcat:3csvkzcgkbbonkaoe23nhqeteu

Next generation micro-power systems

Anantha P. Chandrakasan, Denis C. Daly, Joyce Kwong, Yogesh K. Ramadass
2008 2008 IEEE Symposium on VLSI Circuits  
A major opportunity to reduce the energy consumption of digital circuits is to scale supply voltages to 0.5V and below. The challenges associated with ultra-low-voltage design will be presented.  ...  These include variation-aware design for logic and SRAM circuits, efficient DC-DC converters for ultra-low-voltage delivery, and algorithm structuring to support extreme parallelism.  ...  Variation-Aware Logic Design At low voltages, process variation and reduced I ON /I OFF ratios adversely affect operation of logic circuits.  ... 
doi:10.1109/vlsic.2008.4585930 fatcat:i4hx7zi56zdqfi7gmqsgjqymoa

Design and PVT Analysis of Robust, High Swing Folded Cascode Operational Amplifier

2019 International Journal of Engineering and Advanced Technology  
Thus the designed op amp is low power, high swing and robust towards process, voltage and temperature variations.  ...  Also it is capable of operating at very low voltage up to 0.9V adequately showing reduction in power dissipation.  ...  CMOS transistors are scaled regularly in accordance with Moore's law to achieve significant performance as per various tradeoffs like area, speed, power and design requirements.  ... 
doi:10.35940/ijeat.b2995.129219 fatcat:ylo7ajoqezab7id2iyerck3vsa

Parametric Yield-Driven Resource Binding in High-Level Synthesis with Multi-Vth/VddLibrary and Device Sizing

Yibo Chen, Yu Wang, Yuan Xie, Andres Takach
2012 Journal of Electrical and Computer Engineering  
for low power.  ...  Experimental results show that significant power reduction can be achieved with the proposed variation-aware framework, compared with traditional worstcase based deterministic approaches.  ...  Power consumption and process variability are among other critical design challenges as technology scales.  ... 
doi:10.1155/2012/105250 fatcat:idzsohzc3nci5j7a74hlwvsx44

Guest Editorial Advances in Design of Energy-Efficient Circuits and Systems (Second Issue)

Enrico Macii, Vijaykrishnan Narayanan, Kaushik Roy
2011 IEEE Journal on Emerging and Selected Topics in Circuits and Systems  
Sinha et al. discusses the design of a workload-aware low-power neuromorphic controller for dynamic voltage and frequency scaling in VLSI systems.  ...  ., presents a smart power-saving scheme based on the combination of a sleep model with dynamic voltage scaling.  ... 
doi:10.1109/jetcas.2011.2170596 fatcat:sjns2uegqna5loa4f5xtdhgfs4

A survey of cross-layer power-reliability tradeoffs in multi and many core systems-on-chip

Ahmed A. Eltawil, Michael Engel, Bibiche Geuskens, Amin Khajeh Djahromi, Fadi J. Kurdahi, Peter Marwedel, Smail Niar, Mazen A.R. Saghir
2013 Microprocessors and microsystems  
As systems-on-chip increase in complexity, the underlying technology presents us with significant challenges due to increased power consumption as well as decreased reliability.  ...  Today, designers must consider building systems that achieve the requisite functionality and performance using components that may be unreliable.  ...  In [60] aggressive voltage scaling is applied to embedded memories resulting in low power, high frequency operation, albeit, with errors due to scaling.  ... 
doi:10.1016/j.micpro.2013.07.008 fatcat:bl2v6dfvxnfxnble4pkcg2pcw4
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