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Variation-resilient pipelined timing tracking circuit for SRAM sense amplifier

Zhengping Li, Chunyu Peng, Wenjuan Lu, Lijun Guan, Youwu Tao, Xincun Ji, Junning Chen
<span title="">2016</span> <i title="Institute of Electronics, Information and Communications Engineers (IEICE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/fvf4s3u4inbjpnfv6imirwcvam" style="color: black;">IEICE Electronics Express</a> </i> &nbsp;
A resilient tracking circuit for suppressing the timing variation of SRAM sense amplifier enable (SAE) signal is proposed. Pipelined replica bitline technique is used to favour the desired design.  ...  Simulation results show that the cycle time is reduced by ∼27% owing to ∼70% reduction of the standard deviation of SAE at a 1.05 V supply voltage in 28 nm CMOS technology with four-stage pipeline.  ...  Introduction Sense amplifier (SA), as an important component, is widely used in SRAM design for improving the cycle time, as well as reducing the power dissipation.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1587/elex.13.20150951">doi:10.1587/elex.13.20150951</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/ebso75s5i5cipiymwn7naexyma">fatcat:ebso75s5i5cipiymwn7naexyma</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20181102203129/https://www.jstage.jst.go.jp/article/elex/13/7/13_13.20150951/_pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/3c/35/3c3540b9f37ddc565528a6f72939145119afe689.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1587/elex.13.20150951"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

2018 IndexIEEE Transactions on Very Large Scale Integration (VLSI) SystemsVol. 26

<span title="">2018</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/uqbr2omxsbdgtaxslmblka2nnu" style="color: black;">IEEE Transactions on Very Large Scale Integration (vlsi) Systems</a> </i> &nbsp;
., see 2723-2736 , VLSI Design of an ML-Based Power-Efficient Motion Estimation Controller for Intelligent Mobile Systems; TVLSI Feb. 2018 262-271 Hsieh, Y., see Tsai, Y., TVLSI May 2018 945-957  ...  Hsu, K., Chen, Y., Lee, Y., and Chang, S., Contactless Testing for Prebond Interposers; TVLSI June 2018 1005-1014 Hsu, Y., see Liu, Z., 1565-1574 Hu, J., see Wang, Y., TVLSI May 2018 805-817 Hu, J  ...  Mao, M., +, TVLSI July 2018 1290-1300 Dynamic Choke Sensing for Timing Error Resilience in NTC Systems.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tvlsi.2019.2892312">doi:10.1109/tvlsi.2019.2892312</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/rxiz5duc6jhdzjo4ybcxdajtbq">fatcat:rxiz5duc6jhdzjo4ybcxdajtbq</a> </span>
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2020 Index IEEE Journal of Solid-State Circuits Vol. 55

<span title="">2020</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/cz5rf4o3ezafnl4kjpq643g32e" style="color: black;">IEEE Journal of Solid-State Circuits</a> </i> &nbsp;
., A 32 × 128 SPAD-257 TDC Receiver IC for Pulsed TOF Solid-State 3-D Imaging; JSSC July 2020 1960-1970, see Qi, L., 2889-2901 Jang, S., see Kim, D., JSSC Jan. 2020 167-177 Jansson, J., see Jahromi  ...  ., +, JSSC Oct. 2020 2790-2801 A Capacitor-Coupled Offset-Canceled Sense Amplifier for DRAMs With Reduced Variation of Decision Threshold Voltage.  ...  Joshi, K., +, JSSC Aug. 2020 2151-2160 A Capacitor-Coupled Offset-Canceled Sense Amplifier for DRAMs With Reduced Variation of Decision Threshold Voltage.  ... 
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Review and classification of gain cell eDRAM implementations

Adam Teman, Pascal Meinerzhagen, Andreas Burg, Alexander Fish
<span title="">2012</span> <i title="IEEE"> 2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel </i> &nbsp;
With the increasing requirement of a high-density, high-performance, low-power alternative to traditional SRAM, Gain Cell (GC) embedded DRAMs have gained a renewed interest in recent years.  ...  Several industrial and academic publications have presented GC memory implementations for various target applications, including high-performance processor caches, wireless communication memories, and  ...  Amplifier RBL Clamping, Pipelined Architecture Boosted 3T, PVT tracking read reference feedback, Regulated WBL Half Swing WBL, Stepped WWL Main Design Metric 400 MHz, 70 µs retention  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/eeei.2012.6377022">doi:10.1109/eeei.2012.6377022</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/wrf43obipzeklny4fpnmg5bvky">fatcat:wrf43obipzeklny4fpnmg5bvky</a> </span>
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Circuit Design Advances for Wireless Sensing Applications

Gregory Chen, Scott Hanson, David Blaauw, Dennis Sylvester
<span title="">2010</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/yfvtieuumfamvmjlc255uckdlm" style="color: black;">Proceedings of the IEEE</a> </i> &nbsp;
Recent low-power advances for each of these functions shed light on how ubiquitous sensing can become a reality.  ...  | Miniature wireless sensors with long lifetimes enable new applications for medical diagnosis, infrastructure monitoring, military surveillance, and environmental sensing among many other applications  ...  V TH variations due to random dopant fluctuations (RDF) dominate other sources of variation at such Chen et al.: Circuit Design Advances for Wireless Sensing Applications low voltages.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/jproc.2010.2053333">doi:10.1109/jproc.2010.2053333</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/6szar22lvfhc7crz4ogfntqnlq">fatcat:6szar22lvfhc7crz4ogfntqnlq</a> </span>
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2020 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 67

<span title="">2020</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/l6r6h4xpzvh6jkuzrx565pgwgu" style="color: black;">IEEE Transactions on Circuits and Systems Part 1: Regular Papers</a> </i> &nbsp;
Shi, Q., +, TCSI Dec. 2020 5125-5138 Injection locked amplifiers A Calibration-Free Ring-Oscillator PLL With Gain Tracking Achieving 9% Jitter Variation Over PVT.  ...  El Aroudi, A., +, TCSI May 2020 1729-1739 Electric sensing devices A Self-Timed Voltage-Mode Sensing Scheme With Successive Sensing and Checking for STT-MRAM.  ...  Hsu, Y., +, 48-59 A PVT-Resilient, Highly-Linear Fifth-Order Ring-Oscillator-Based Filter.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tcsi.2021.3055003">doi:10.1109/tcsi.2021.3055003</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/kbmst5td2bbvtl7vpbj3knnkri">fatcat:kbmst5td2bbvtl7vpbj3knnkri</a> </span>
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2020 Index IEEE Transactions on Very Large Scale Integration (VLSI) Systems Vol. 28

<span title="">2020</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/uqbr2omxsbdgtaxslmblka2nnu" style="color: black;">IEEE Transactions on Very Large Scale Integration (vlsi) Systems</a> </i> &nbsp;
., Conflux-An Asynchronous Two-to-One Multiplexor for Time-Division Multiplexing and Clockless, Tokenless Readout; TVLSI Feb. 2020 503-515 Holcomb, D., see 2685-2698 Holcomb, D.E., see 1807-1820 Homayoun  ...  ., +, TVLSI Dec. 2020 2636-2649 Content-addressable storage ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs.  ...  ., +, TVLSI March 2020 818-822 A Maximum-Eye-Tracking CDR With Biased Data-Level and Eye Slope Detector for Near-Optimal Timing Adaptation.  ... 
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2019 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 66

<span title="">2019</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/l6r6h4xpzvh6jkuzrx565pgwgu" style="color: black;">IEEE Transactions on Circuits and Systems Part 1: Regular Papers</a> </i> &nbsp;
TCSI May 2019 1840-1852 Hybrid Latch-Type Offset Tolerant Sense Amplifier for Low-Voltage SRAMs.  ...  ., +, TCSI June 2019 2037-2050 Hybrid Latch-Type Offset Tolerant Sense Amplifier for Low-Voltage SRAMs.  ...  Analysis of SRAM Enhancements Through Sense Amplifier  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tcsi.2020.2966967">doi:10.1109/tcsi.2020.2966967</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/f663jj5g45e3peggn3gwn5jys4">fatcat:f663jj5g45e3peggn3gwn5jys4</a> </span>
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SOCC 2019 Author Index

<span title="">2019</span> <i title="IEEE"> 2019 32nd IEEE International System-on-Chip Conference (SOCC) </i> &nbsp;
Amplifier with Peaking-Dedicated Inductor in 65- Nm CMOS Gadi, Vijit F1A.5 Embedded 6-T SRAM with Novel Self-Adaptive Write Enhance Scheme for Improved Fmax Gan, Jiayan W3C.3 181 A Power-Efficient  ...  Minimum Energy Real Time Tasks Using Geometric Programming Herkersdorf, Andreas T2B.3 406 Register Requirement Minimization of Fixed-Depth Pipelines for Streaming Data Applications Hiratsuka,  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/socc46988.2019.9088078">doi:10.1109/socc46988.2019.9088078</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/wzmgb42mjzbu5hvgccttlhw3zu">fatcat:wzmgb42mjzbu5hvgccttlhw3zu</a> </span>
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2019 Index IEEE Journal of Solid-State Circuits Vol. 54

<span title="">2019</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/cz5rf4o3ezafnl4kjpq643g32e" style="color: black;">IEEE Journal of Solid-State Circuits</a> </i> &nbsp;
., +, JSSC Dec. 2019 3336-3347 CMOS logic circuits A 28-nm 320-Kb TCAM Macro Using Split-Controlled Single-Load 14T Cell and Triple-Margin Voltage Sense Amplifier.  ...  Cai, Y., +, JSSC Feb. 2019 550-559 CMOS memory circuits A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/jssc.2019.2956675">doi:10.1109/jssc.2019.2956675</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/laiuae7dtragjijttgfatsldmu">fatcat:laiuae7dtragjijttgfatsldmu</a> </span>
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2018 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 65

<span title="">2018</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/l6r6h4xpzvh6jkuzrx565pgwgu" style="color: black;">IEEE Transactions on Circuits and Systems Part 1: Regular Papers</a> </i> &nbsp;
., +, TCSI Sept. 2018 3014-3026 HTD: A Light-Weight Holosymmetrical Transition Detector for Wide-Voltage-Range Variation Resilient ICs.  ...  ., +, TCSI Aug. 2018 2389-2402 A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits.  ... 
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A Survey of Near-Data Processing Architectures for Neural Networks [article]

Mehdi Hassanpour, Marc Riera, Antonio González
<span title="2021-12-23">2021</span> <i > arXiv </i> &nbsp; <span class="release-stage" >pre-print</span>
In this paper, we present a survey of techniques for designing NDP architectures for NN.  ...  Emerging memory technologies, such as ReRAM and 3D-stacked, are promising for efficiently architecting NDP-based accelerators for NN due to their capabilities to work as both: High-density/low-energy storage  ...  Fig. 12 shows an example of the SRAM circuit for shows an example of a bitwise NOT using a DCC.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener" href="https://arxiv.org/abs/2112.12630v1">arXiv:2112.12630v1</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/drkwrztkazd3hlblxc7i4kgn2a">fatcat:drkwrztkazd3hlblxc7i4kgn2a</a> </span>
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2021 Index IEEE Transactions on Very Large Scale Integration (VLSI) Systems Vol. 29

<span title="">2021</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/uqbr2omxsbdgtaxslmblka2nnu" style="color: black;">IEEE Transactions on Very Large Scale Integration (vlsi) Systems</a> </i> &nbsp;
The Author Index contains the primary entry for each item, listed under the first author's name.  ...  Zhuang, H., +, TVLSI July 2021 1485-1489 Amplifiers A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation.  ...  Venugopal Rao, V., +, TVLSI Dec. 2021 2013-2026 Analog-digital conversion A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tvlsi.2021.3136367">doi:10.1109/tvlsi.2021.3136367</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/fwqswbyzejgfhgbzywrvsf2qgi">fatcat:fwqswbyzejgfhgbzywrvsf2qgi</a> </span>
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An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power

Riduan Khaddam-Aljameh, Pier-Andrea Francese, Luca Benini, Evangelos Eleftheriou
<span title="">2020</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/uqbr2omxsbdgtaxslmblka2nnu" style="color: black;">IEEE Transactions on Very Large Scale Integration (vlsi) Systems</a> </i> &nbsp;
Its operation principle is based on first converting an SRAM-stored n-bit weight into a proportional voltage using a pipeline D/A converter built from n + 1 equally sized stages.  ...  With our proposed architecture, the required circuit area, computation time, and power consumption scale linearly versus the bit resolution of both the inputs and the weights.  ...  Bezerra for the constructive discussions.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tvlsi.2020.3037871">doi:10.1109/tvlsi.2020.3037871</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/axpqq2gjdfgl7jmn7ew4lxvcmy">fatcat:axpqq2gjdfgl7jmn7ew4lxvcmy</a> </span>
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Architecture support for disciplined approximate programming

Hadi Esmaeilzadeh, Adrian Sampson, Luis Ceze, Doug Burger
<span title="2012-04-18">2012</span> <i title="Association for Computing Machinery (ACM)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/35q3ync5nbhnjfpylznlz57lyi" style="color: black;">SIGARCH Computer Architecture News</a> </i> &nbsp;
The basis of our design is dual-voltage operation, with a high voltage for precise operations and a low voltage for approximate operations.  ...  Acknowledgments We would like to thank the anonymous reviewers for their valuable comments.  ...  We also thank Sied Mehdi Fakhraie, Jacob Nelson, Behnam Robatmili, and the members of the Sampa group for their feedback on the manuscript.  ... 
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