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Variation-Aware Pipelined Cores through Path Shaping and Dynamic Cycle Adjustment

Ioannis Tsiokanos, Lev Mukhanov, Dimitrios S. Nikolopoulos, Georgios Karakonstantis
2018 Proceedings of the International Symposium on Low Power Electronics and Design - ISLPED '18  
The integrated LLP s prediction unit and the dynamic cycle adjustment avoid such failures and any quality loss at a cost of up-to 0.61% throughput and 0.3% area overheads, while saving 37.95% power on  ...  When applied to the implementation of an IEEE-754 compatible double precision floating-point unit (FPU) in a 45nm process technology, the path shaping helps to reduce the bit error rates on average by  ...  ACKNOWLEDGEMENTS The presented work is partially supported by the European Commission Horizon 2020 programme under grant no. 688540 (UniServer) and grant no. 732631 (OPRECOMP).  ... 
doi:10.1145/3218603.3218617 dblp:conf/islped/TsiokanosMNK18 fatcat:smwvykzuvnemtdxebyrifzp7ki

Low-Power Variation-Aware Cores based on Dynamic Data-Dependent Bitwidth Truncation

Ioannis Tsiokanos, Lev Mukhanov, Georgios Karakonstantis
2019 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)  
To facilitate the adoption of such a scheme within pipelined cores and limit the incurred overheads, we also shape the path distribution appropriately for isolating the LLPs in a single pipeline stage.  ...  When applied to the implementation of an IEEE-754 compatible double precision floating-point unit (FPU) in a 45nm technology, our approach eliminates timing failures under 8% delay variations with no performance  ...  ACKNOWLEDGMENTS The presented research effort is partially supported by the European Community Horizon 2020 programme under grant no. 688540 (UniServer) and grant no. 732631 (OPRECOMP).  ... 
doi:10.23919/date.2019.8714942 dblp:conf/date/TsiokanosMK19 fatcat:6awllh7v6bfa7j4sa3apn6x4mi

Significance-Driven Data Truncation for Preventing Timing Failures

Ioannis Tsiokanos, Lev Mukhanov, Dimitrios S. Nikolopoulos, Georgios Karakonstantis
2019 IEEE transactions on device and materials reliability  
assumed 8.1% variation-induced worst-case path delay increase in a 45 nm process.  ...  When applied to an IEEE-754 compatible double precision Floating Point Unit (FPU), the proposed approach reduces the timing failures by 216.25× on average compared to the reference FPU design under an  ...  variation-aware IEEE-754 compatible [22] Floating Point Unit (FPU) in a 45 nm process technology.  ... 
doi:10.1109/tdmr.2019.2898949 fatcat:evi3wade2fgmjbjnicupszfwn4

Bundle Adjustment — A Modern Synthesis [chapter]

Bill Triggs, Philip F. McLauchlan, Richard I. Hartley, Andrew W. Fitzgibbon
2000 Lecture Notes in Computer Science  
Bundle adjustment is the problem of refining a visual reconstruction to produce jointly optimal structure and viewing parameter estimates.  ...  This paper is a survey of the theory and methods of photogrammetric bundle adjustment, aimed at potential implementors in the computer vision community.  ...  / path through the states.  ... 
doi:10.1007/3-540-44480-7_21 fatcat:jm2ewshh5bejhnv5dixghvp6y4

Enhancing the Efficiency of Energy-Constrained DVFS Designs

Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori
2013 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
A dedicated core can be added for low-energy operation, but has a high cost in terms of area and leakage.  ...  Index Terms-Context-aware design, dynamic voltage and frequency scaling, lifetime energy reduction, low-power design.  ...  Fig. 10 .Fig. 11 . 1011 Layout of floating point front-end unit (FFU) module (a) without replication and (b) with replication.  ... 
doi:10.1109/tvlsi.2012.2219084 fatcat:oziivetnvnfftkbfyukbri5ck4

Robust and resilient designs from the bottom-up: Technology, CAD, circuit, and system issues

Vijay Janapa Reddi, David Z. Pan, Sani R. Nassif, Keith A. Bowman
2012 17th Asia and South Pacific Design Automation Conference  
As technology scales, the adverse impact of these variations on system-level metrics increases.  ...  The semiconductor industry is facing a critical research challenge: design future high performance and energy efficient systems while satisfying historical standards for reliability and lower costs.  ...  Post-silicon calibration of the buffer delay chain ensures the TRC always fails if any critical path fails in the pipeline stage due to a dynamic variation.  ... 
doi:10.1109/aspdac.2012.6165064 dblp:conf/aspdac/ReddiPNB12 fatcat:khckyzmudvc6xfx2lgclvhioke

Timing analysis of erroneous systems

Omid Assare, Rajesh Gupta
2014 Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis - CODES '14  
In order to enable reliable timing analysis of large programs, we propose Clustered Timing Model (CTM), a high level timing model based on clustering functionally similar timing paths of the processor,  ...  The accuracy of the model is verified using our variation-aware timing analysis framework with an average error of 3.9% (max. 6.7%) across a wide range of voltage-temperature corners.  ...  For example, previously developed CTMs for Integer Unit, Floating-Point Unit, and Co-Processors of a processor could be combined to obtain a new unified CTM.  ... 
doi:10.1145/2656075.2656101 dblp:conf/codes/AssareG14 fatcat:bskxaf6j5nfnbkj3ca537q6k6a

The circuit and physical design of the POWER4 microprocessor

J. D. Warnock, J. M. Keaty, J. Petrovick, J. G. Clabes, C. J. Kircher, B. L. Krauter, P. J. Restle, B. A. Zoric, C. J. Anderson
2002 IBM Journal of Research and Development  
It contains two microprocessor cores, high-speed buses, and an on-chip memory subsystem.  ...  Similarly, at the unit, core, and chip levels, floorplanning and even timing can begin in parallel with the higher-level logic design and simulation.  ...  Acknowledgments The authors wish to acknowledge all of our colleagues on the POWER4 design team, as well as many others in IBM who have contributed to the POWER4 design.  ... 
doi:10.1147/rd.461.0027 fatcat:wp4ojp7zyfam5nhtajbfdfh2uy

Exploring circuit timing-aware language and compilation

Giang Hoang, Robby Bruce Findler, Russ Joseph
2011 Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems - ASPLOS '11  
By adjusting the design of the ISA and enabling circuit timingsensitive optimizations in a compiler, we can more effectively exploit timing speculation.  ...  Furthermore, by selectively replacing these codes with instruction sequences which are semantically equivalent but reduce activity on timing critical circuit paths, we can trigger fewer timing errors and  ...  Acknowledgments We would like to thank anonymous reviewers and Antonio Gonzalez for their helpful comments. This work is in part supported by NSF CAREER CCF-0644332 and NSF CNS-0720820.  ... 
doi:10.1145/1950365.1950405 dblp:conf/asplos/HoangFJ11 fatcat:neio2onoc5efxiillofquxcgb4

Performance Analysis of Timing-Speculative Processors

Omid Assare, Rajesh Gupta
2021 IEEE transactions on computers  
I am grateful for the freedom I had to explore and change direction and the opportunity to learn and practice independent thinking. It has been an honor to work under his supervision.  ...  For example, previously developed CTMs for Integer Unit, Floating-Point Unit, and Co-Processors of a processor could be combined to obtain a new unified CTM.  ...  For instance conventional dynamic voltage and frequency scaling (DVFS) adjusts the system's operating point based on pre-characterized safe values stored in a look-up table [60] [56] .  ... 
doi:10.1109/tc.2021.3051877 fatcat:nkkie5fnx5hybmnjaf52qux36y

SISPO: Space Imaging Simulator for Proximity Operations [article]

Mihkel Pajusalu and Iaroslav Iakubivskyi and Gabriel Jörg Schwarzkopf and Olli Knuuttila and Timo Väisänen and Maximilian Bührer and Hans Teras and Guillaume Le Bonhomme and Mario F. Palos and Jaan Praks and Andris Slavinskis
2021 arXiv   pre-print
The simulator concentrates on realistic surface rendering and has supplementary models to produce realistic dust- and gas-environment optical models for comets and active asteroids.  ...  This paper describes the architecture and demonstrates the capabilities of a newly developed, physically-based imaging simulator environment called SISPO, developed for small solar system body fly-by and  ...  It hosted the Hayabusa spacecraft on its surface in 2005.  ... 
arXiv:2105.06771v2 fatcat:mhkw37tznbhhrf7qeen6ndr26m

Technologies for Ultradynamic Voltage Scaling

A.P. Chandrakasan, D.C. Daly, D.F. Finchelstein, J. Kwong, Y.K. Ramadass, M.E. Sinangil, V. Sze, N. Verma
2010 Proceedings of the IEEE  
Trend in minimum energy point of a 32 b adder with process scaling using predictive models [31].  ...  Second, we describe a 0.3 V 16-bit microcontroller with on-chip SRAM, where the supply voltage is generated efficiently by an integrated dc-dc converter. Fig. 5.  ...  Acknowledgment The authors would like to acknowledge Dimitri Antoniadis, Yu Cao, Eric Wang, and Wei Zhao for help with predictive technology models.  ... 
doi:10.1109/jproc.2009.2033621 fatcat:ehsup4tsbfa67ccdre7wvt26yq

Microarchitecture Design [chapter]

2016 Electronic Design Automation for IC System Design, Verification, and Testing  
The weight of a path/cycle is defined as the sum of weights of all edges on the path/cycle.  ...  The changes required in this stage are adjustments to the functional unit and the data cache (dl1 and l2) access latencies.  ... 
doi:10.1201/b19569-15 fatcat:vekug75yire5vldpb4xx6y5ooq

Robust shared autonomy for mobile manipulation with continuous scene monitoring

Wolfgang Merkt, Yiming Yang, Theodoros Stouraitis, Christopher E. Mower, Maurice Fallon, Sethu Vijayakumar
2017 2017 13th IEEE Conference on Automation Science and Engineering (CASE)  
Our system is flexible to be adapted to new robotic systems, and we demonstrate our work on two real-world platformsfixed and floating base -in shared workspace scenarios.  ...  The particular motion sequences are composed automatically based on high-level objectives provided by a human operator, with continuous scene monitoring during execution automatically detecting and adapting  ...  Furthermore, in the case of multiple objects, it automatically determines whether both are reachable simultaneously through optimized base positioning using iDRM, and it leverages the floating base to  ... 
doi:10.1109/coase.2017.8256092 dblp:conf/case/MerktYSMFV17 fatcat:2phiai7bzrhhnitzwv3avdxkeq

Modeling and Characterizing Power Variability in Multicore Architectures

Ke Meng, Frank Huebbers, Russ Joseph, Yehea Ismail
2007 2007 IEEE International Symposium on Performance Analysis of Systems & Software  
The impact of random variation in physical factors such as gate length and interconnect spacing will have a profound impact on not only performance of chips, but also their power behavior.  ...  We introduce VariPower, a tool for modeling power variability based on an microarchitectural description and floorplan of a chip.  ...  Acknowledgments We would like to thank the anonymous reviewers for their constructive feedback and helpful suggestions. This work was supported in part by NSF award CCF-0541337.  ... 
doi:10.1109/ispass.2007.363745 dblp:conf/ispass/MengHJI07 fatcat:miphfyj3dbhlnpkak3aq2uauxq
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