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Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors

Radu Teodorescu, Josep Torrellas
2008 2008 International Symposium on Computer Architecture  
This paper proposes variation-aware algorithms for application scheduling and power management.  ...  Within-die process variation causes individual cores in a Chip Multiprocessor (CMP) to differ substantially in both static power consumed and maximum frequency supported.  ...  Interestingly, the technology for variation-aware application scheduling and power management is now available.  ... 
doi:10.1109/isca.2008.40 dblp:conf/isca/TeodorescuT08 fatcat:ee4pwccxgndobkqi4llwnujxky

Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors

Radu Teodorescu, Josep Torrellas
2008 SIGARCH Computer Architecture News  
This paper proposes variation-aware algorithms for application scheduling and power management.  ...  Within-die process variation causes individual cores in a Chip Multiprocessor (CMP) to differ substantially in both static power consumed and maximum frequency supported.  ...  Interestingly, the technology for variation-aware application scheduling and power management is now available.  ... 
doi:10.1145/1394608.1382152 fatcat:poxno7qg4zanhgqnetulnhdy4q

Power management of variation aware chip multiprocessors

Abu Saad Papa, Madhu Mutyam
2008 Proceedings of the 18th ACM Great Lakes symposium on VLSI - GLSVLSI '08  
CMPs have become a common way of reducing chip complexity and power consumption while maintaining high performance.  ...  As technology continues to scale, inter-die and intra-die variations in process parameters can result in significant impact on performance and power consumption, leading to asymmetry among the cores that  ...  The traditional scheduling techniques need to be revisited and new techniques have to be evolved for efficient power management of chip multiprocessors.  ... 
doi:10.1145/1366110.1366211 dblp:conf/glvlsi/PapaM08 fatcat:2ltk2pkcozca5dqxip6pwxjpuq

Thermal energy aware proportionate scheduler for multiprocessor systems

Ramesh Pasupuleti, Ramachandraiah Uppu
2018 International Journal of Engineering & Technology  
This article presents Thermal Energy aware proportionate scheduler (TEAPS) to reduce leakage power consumption.  ...  As per Moore's law, the power consumption and heat solidity of the multiprocessor systems are increasing proportionately.  ...  This paper offers a thermal energy aware scheduling mechanism to minimize the leakage power consumption in the multiprocessor system.  ... 
doi:10.14419/ijet.v7i3.13278 fatcat:x6fk42yvyzap5bc3nzh5g4z2wm

Thermal Analysis of Fair Scheduling in Real-time Embedded Systems

Tayyaba Bokhari, Sajjad Haider Shami, Farhan Haseeb
2018 International Journal of Reconfigurable and Embedded Systems (IJRES)  
Over the past few decades, increased demand of highly sophisticated real-time applications with complex functionalities has directly led to exponentially increased power consumption and significantly elevated  ...  In related literature, the introduction of fairness is often considered as a tool to achieve optimality in multiprocessor scheduling algorithms.  ...  Another temperature aware task scheduling technique for hard real-time applications in MPSoCs is proposed by Chantem et al.  ... 
doi:10.11591/ijres.v7.i1.pp48-56 fatcat:uxl5zdhaqjd4ljlz2e45ra7ixe

VEBoC: Variation and error-aware design for billions of devices on a chip

Shoaib Akram, Scott Cromar, Gregory Lucas, Alexandros Papakonstantinou, Deming Chen
2008 2008 Asia and South Pacific Design Automation Conference  
We elaborate on variation-aware synthesis, holistic error modeling, reliable multicore, and synthesis for application-specific multicore.  ...  Meanwhile, designers also face severe on-chip parameter variations, soft/hard errors, and high leakage power.  ...  The design of interconnection network, cache hierarchy, memory consistency model, bandwidth requirements, and power management are interrelated in the design of chip multiprocessors as shown in [12] .  ... 
doi:10.1109/aspdac.2008.4484062 dblp:conf/aspdac/AkramCLPC08 fatcat:jzvvrtwjizbinkn3s5wkzfbvqm

Scheduling Based Energy Optimization Technique

Sampath Nayak
2020 International Journal for Research in Applied Science and Engineering Technology  
At the operating system level, multi-core and multiprocessor system on chip started a new computing era but brought various twofold scheduling challenges in current developed thermal aware algorithms for  ...  An offline thermal aware scheduling algorithm is proposed for improvement in multi core embedded system in case of energy, reliability and performance of a multi core system has been introduced.  ...  multiprocessor system on chip.  ... 
doi:10.22214/ijraset.2020.6152 fatcat:ya3djnmi25fcnjfahfei2djv4a

Thermal-Aware Scheduling for Future Chip Multiprocessors

Kyriakos Stavrou, Pedro Trancoso
2007 EURASIP Journal on Embedded Systems  
In this paper, we analyze the evolution of the thermal issues for the future chip multiprocessor architectures and show that as the number of on-chip cores increases, the thermal-induced problems will  ...  Nevertheless, the integration of several cores onto the same chip may lead to increased heat dissipation and consequently additional costs for cooling, higher power consumption, decrease of the reliability  ...  The simulator The simulator used is the Thermal Scheduling SImulator for Chip Multiprocessors (TSIC) [29] , which has been developed specially to study thermal-aware scheduling on chip multiprocessors  ... 
doi:10.1155/2007/48926 fatcat:m74lyiczcjdo3cw2ko5vokeku4

Thermal-Aware Scheduling for Future Chip Multiprocessors

Kyriakos Stavrou, Pedro Trancoso
2007 EURASIP Journal on Embedded Systems  
In this paper, we analyze the evolution of the thermal issues for the future chip multiprocessor architectures and show that as the number of on-chip cores increases, the thermal-induced problems will  ...  Nevertheless, the integration of several cores onto the same chip may lead to increased heat dissipation and consequently additional costs for cooling, higher power consumption, decrease of the reliability  ...  The simulator The simulator used is the Thermal Scheduling SImulator for Chip Multiprocessors (TSIC) [29] , which has been developed specially to study thermal-aware scheduling on chip multiprocessors  ... 
doi:10.1186/1687-3963-2007-048926 fatcat:p6vgj4k2y5de7pcvstiubggnbe

Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy

Jianbo Dong, Lei Zhang, Yinhe Han, Guihai Yan, Xiaowei Li
2009 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing  
Process variation causes core-to-core (C2C) performance asymmetry across a chip, which should be taken into consideration for application scheduling.  ...  Thread-Level Redundancy in Chip Multiprocessors (TLR-CMP) is efficient for soft error tolerance.  ...  Teodorescu and Torrellas [5] compared various variationaware algorithms for application scheduling and power management.  ... 
doi:10.1109/prdc.2009.12 dblp:conf/prdc/DongZHYL09 fatcat:bxj2ifjmjndazed2db22tkuvjq

Temperature Aware Task Scheduling in MPSoCs

Ayse Kivilcim Coskun, Tajana Simunic Rosing, Keith Whisnant
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
In this work, we explore the benefits of thermally aware task scheduling for multiprocessor systems-on-a-chip (MPSoC).  ...  This way, hot spots and temperature variations are decreased, and the performance cost is significantly reduced.  ...  Acknowledgements This work has been funded by Sun Microsystems, and the University of California MICRO grant 06-198.  ... 
doi:10.1109/date.2007.364540 fatcat:xc4rt3xhrfb3jpl7wiywawlpcu

CPM in CMPs: Coordinated Power Management in Chip-Multiprocessors

Asit K. Mishra, Shekhar Srikantaiah, Mahmut Kandemir, Chita R. Das
2010 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis  
Our first-tier consists of a global power manager that allocates power targets to individual islands based on the workload dynamics.  ...  The power consumptions of these islands are in turn controlled by a secondtier, consisting of local controllers that regulate island power using dynamic voltage and frequency scaling in response to workload  ...  Acknowledgement The authors would like the thank the anonymous reviewers for their comments.  ... 
doi:10.1109/sc.2010.15 dblp:conf/sc/MishraSKD10 fatcat:ovogo5hiozaanofvb7zpx2yi34

Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling

Jianbo Dong, Lei Zhang, Yinhe Han, Guihai Yan, Xiaowei Li
2010 Journal of systems architecture  
Thread-level redundancy is an efficient approach for transient fault detection and recovery in Chip Multiprocessors (CMPs), in which two adjacent cores are statically coupled to form a functional Dual  ...  We call them inter-and intra-pair asymmetries, respectively, both of which should be taken into considerations in application scheduling for CMPs with static core coupling.  ...  Teodorescu and Torrellas [5] compared various variation-aware algorithms for application scheduling and power management.  ... 
doi:10.1016/j.sysarc.2010.09.003 fatcat:vnaxn3i36naqlcpn3qwass3yhq

Ec-A: A Task Allocation Algorithm For Energy Minimization In Multiprocessor Systems

Anju S. Pillai, T.B. Isha
2014 Zenodo  
With the necessity of increased processing capacity with less energy consumption; power aware multiprocessor system has gained more attention in the recent future.  ...  This paper presents a novel task dependent job allocation algorithm: Energy centric- Allocation (Ec-A) and Rate Monotonic (RM) scheduling to minimize energy consumption in a multiprocessor system.  ...  Out of these techniques, energy aware task scheduling is one of the prime. A reliability aware energy management is proposed in [17] .  ... 
doi:10.5281/zenodo.1091689 fatcat:62vtfm2be5cnrcsxuvmjwachqy

Predictive modeling based power estimation for embedded multicore systems

Sriram Sankaran
2016 Proceedings of the ACM International Conference on Computing Frontiers - CF '16  
Further, the unique characteristics of these systems provide numerous opportunities for power management which require models for power estimation.  ...  In this work, a statistical approach that models the impact of the individual cores and memory hierarchy on overall power consumed by Chip Multiprocessors is developed using Performance Counters.  ...  In our model, we consider a particular class of multicore systems called the Chip Multiprocessors. Figure 1 describes a Chip Multiprocessor.  ... 
doi:10.1145/2903150.2911714 dblp:conf/cd/Sankaran16 fatcat:laqycfmrmrbzjaj5eti6y6oezi
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