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Variability-aware and fault-tolerant self-adaptive applications for many-core chips
2013
2013 18TH IEEE EUROPEAN TEST SYMPOSIUM (ETS)
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In this paper, an high-level method is proposed to map and manage a parallel application on an unreliable many-cores processor System on Chip subject to intra-die variability. ...
In this context, high energy efficiency will be available, under the constraint that applications leverage the large amount of computing cores, while masking frequent faults of the chip. ...
Index Terms-Self-Adaptive, Self-Mapping, Distributed applications, Multiprocessor Systems, Many-cores Processor, System on Chip, Variability-Aware, Energy-aware systems
I. ...
doi:10.1109/ets.2013.6569379
dblp:conf/ets/BizotCZN13
fatcat:dqvwl7tnmfazhehz3vn3dvznp4
Variability-aware and fault-tolerant self-adaptive applications for many-core chips
2013
2013 IEEE 19th International On-Line Testing Symposium (IOLTS)
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In this paper, an high-level method is proposed to map and manage a parallel application on an unreliable many-cores processor System on Chip subject to intra-die variability. ...
In this context, high energy efficiency will be available, under the constraint that applications leverage the large amount of computing cores, while masking frequent faults of the chip. ...
Index Terms-Self-Adaptive, Self-Mapping, Distributed applications, Multiprocessor Systems, Many-cores Processor, System on Chip, Variability-Aware, Energy-aware systems
I. ...
doi:10.1109/iolts.2013.6604048
dblp:conf/iolts/BizotCZN13
fatcat:altravhssnhkvnlbiem7doqjxq
Guest Editorial: Bio-inspired Hardware and Evolvable Systems
2018
IET Computers & Digital Techniques
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New concerns are variability, power consumption, heat dissipation and reliability, with system architectures moving towards system-on-chip, many-core, and heterogeneity. ...
improve hardware fault tolerance and autonomous self-repair. ...
New concerns are variability, power consumption, heat dissipation and reliability, with system architectures moving towards system-on-chip, many-core, and heterogeneity. ...
doi:10.1049/iet-cdt.2018.0073
fatcat:2t4pqqkjhjdvxok2ai3fmjobwa
Biologically Inspired Robust Tera-Device Processors
2012
IEEE Design & Test of Computers
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These approaches guarantee a fault-tolerant, congestion-free, and deadlock-free routing, as well as a variability-aware, power-aware, and application-deadline-aware faulttolerant task scheduling and allocation ...
The algorithm is further extended to enable variability-aware and power-aware task scheduling and allocation. ...
doi:10.1109/mdt.2012.2211174
fatcat:rfl2pmrkrbgpbgetykpgz5brxi
Underdesigned and Opportunistic Computing in Presence of Hardware Variability
2013
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This leads to the vision of underdesigned hardware that utilizes a software stack that opportunistically adapts to a sensed or modeled hardware. ...
These variations have led to increasing use of overdesign and guardbands in design and test to ensure yield and reliability with respect to a rigid set of datasheet specifications. ...
In addition, many applications have inherent algorithmic and cognitive error tolerance. ...
doi:10.1109/tcad.2012.2223467
fatcat:gtncdvvjvvgjth6ihii7y24g54
Design and architectures for dependable embedded systems
2011
Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '11
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In addition, we present a new classification on faults, errors, and failures. ...
The paper presents an overview of a major research project on dependable embedded systems that has started in Fall 2010 and is running for a projected duration of six years. ...
Furthermore, we would like to thank Philip Axer (TU Braunschweig), Thomas Ebi (KIT), and Holm Rauchfuss (TUM) for support in preparing this paper. ...
doi:10.1145/2039370.2039384
dblp:conf/codes/HenkelBBBBCEEHHHKLMPRSSTTWW11
fatcat:jrd25bf65nfjxbuuuvy3bz6zsm
Massively Parallel Processor Architectures for Resource-aware Computing
[article]
2014
arXiv
pre-print
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., power consumption, reliability, resource management, as well as application parallelization and mapping), TCPAs are inherently designed in a way to support self-adaptivity and resource awareness at ...
These programmable accelerators are well suited for domain-specific computing from the areas of signal, image, and video processing as well as other streaming processing applications. ...
Therefore, providing a fault tolerance solution for processor arrays on demand and (a) with little timing and area overheads, (b) aware of the running application and sensitivity of system towards errors ...
arXiv:1405.2907v1
fatcat:uardefsilngdnbllkg5qkmsxha
DeSyRe: On-demand system reliability
2013
Microprocessors and microsystems
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As fabrication technology scales down, chips are becoming less reliable, thereby incurring increased power and performance costs for fault tolerance. ...
The DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). ...
• Adaptive check-pointing (i.e. rollback and recover).o Application-aware o Adapted to fault density • Self-correcting mechanisms at the components (i.e. ...
doi:10.1016/j.micpro.2013.08.008
fatcat:jg623r4hmngthk652u7qi6ibme
Cross-layer virtual observers for embedded multiprocessor system-on-chip (MPSoC)
2012
Proceedings of the 11th International Workshop on Adaptive and Reflective Middleware - ARM '12
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We demonstrate the effectiveness and applicability of these concepts specifically overcoming the vulnerabilities introduced by faults and process variability using two case studies: one using virtual observer ...
Cross-layer resilient systems, which distribute the responsibility for tolerating errors, device variation, and aging across the system stack, have the potential to provide the resilience required to implement ...
ACKNOWLEDGEMENT This material is based on work supported by the NSF under awards CCF-1029783 (Variability Expedition) and CNS-1063596. ...
doi:10.1145/2405679.2405683
dblp:conf/middleware/SarmaDV12
fatcat:bvbi4gh3mvbddogq4xme2kz2qi
Variability-aware memory management for nanoscale computing
2013
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)
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This paper discusses the concept of variability-aware memory management for nanoscale computing systems. ...
As a result, it is imperative for designers to build variation-aware software stacks that may adapt and opportunistically exploit said variations to increase system performance/responsiveness as well as ...
ACKNOWLEDGMENT This work was partially supported by NSF Variability Expedition Grant Numbers CCF-1029783 and CCF-1029030. ...
doi:10.1109/aspdac.2013.6509584
dblp:conf/aspdac/DuttGNBG13
fatcat:3csvkzcgkbbonkaoe23nhqeteu
2019 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 38
2019
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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., and Zorian, Y. ...
., +, TCAD June 2019 1003-1016 ShuttleNoC: Power-Adaptable Communication Infrastructure for Many-Core Processors. ...
SWIFT: Switch-Level Fault Simulation on GPUs. Schneider, E., +, TCAD Jan. 2019 122-135 Fault tolerance Adaptive 3D-IC TSV Fault Tolerance Structure Generation. ...
doi:10.1109/tcad.2020.2964359
fatcat:qjr6i73tkrgnrkkmtjexbxberm
Reliability-Aware Resource Management in Multi-/Many-Core Systems: A Perspective Paper
2021
Journal of Low Power Electronics and Applications
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However, the optimal allocation of applications/tasks on multi/many-core platforms is an increasingly complex problem. ...
This article presents a survey of recent works that focus on reliability-aware resource management in multi-/many-core systems. ...
Reliability-Aware Resource Management in Multi-/Many-Core Systems Given the variety of applications executed on multi-/many-core systems, optimal allocation of on-chip resources is an increasingly complex ...
doi:10.3390/jlpea11010007
fatcat:uvzwnfrprne7lbd2fg2goh3v2q
Self-Awareness in Systems on Chip - A Survey
2017
Zenodo
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This project has received funding from the European Union's Horizon 2020 research and innovation programme under the Marie Curie grant agreement No 705617. ...
The traditional metrics of performance, power, energy, cost and fault tolerance are well understood. ...
Self-Awareness on Chip Features of self-awareness have found their way in many SoC resource management solutions. ...
doi:10.5281/zenodo.1488204
fatcat:uepgzlnfyzezfeblvcpyshm4om
A Middleware Approach to Achieving Fault Tolerance of Kahn Process Networks on Networks on Chips
2011
International Journal of Reconfigurable Computing
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We also list our ideas on the development of a simulation platform as an initial step towards creating fault tolerance strategies for KPNs applications running on NoCs. ...
With this work, we also provide a methodology that can help in identifying the requirements and implementing fault tolerance and adaptivity support on real platforms. ...
Our eventual goal is to run a KPN application directly on an NoC platform with self-adaptivity and fault-tolerance features. ...
doi:10.1155/2011/295385
fatcat:x4fhqxeu5bebtjx3or6beucihm
Fault tolerance on-chip: a reliable computing paradigm using self-test, self-diagnosis, and self-repair (3S) approach
2018
Science China Information Sciences
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Fault tolerance on-chip: a reliable computing paradigm using self-test, self-diagnosis, and self-repair (3S) approach. ...
The "magic cure" is the Fault Tolerance On-Chip (FTOC) mechanism, which relies on a suite of built-in design-for-reliability logic, including fault detection, fault diagnosis, and error recovery, working ...
Beyond conventional fault tolerance computing [1] , Fault Tolerance On-Chip (FTOC) faces several unique challenges: (1) Resourcelimited. ...
doi:10.1007/s11432-017-9290-4
fatcat:3mwg4l5pyrashe6het5rlsnlue
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