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Variability in architectural simulations of multi-threaded workloads

A.R. Alarneldeen, D.A. Wood
The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings.  
In a central result of this paper, we show that variability in multi-threaded commercial workloads can lead to incorrect architectural conclusions (e.g., 31% of the time in one experiment).  ...  Multi-threaded commercial workloads implement many important internet services.  ...  Acknowledgments We thank Milo Martin and Dan Sorin who were the first to advocate multiple simulations to deal with variability.  ... 
doi:10.1109/hpca.2003.1183520 dblp:conf/hpca/AlameldeenW03 fatcat:b3atn7n5ajdo3hkgr7dvz2am6y

BarrierPoint: Sampled simulation of multi-threaded applications

Trevor E. Carlson, Wim Heirman, Kenzo Van Craeynest, Lieven Eeckhout
2014 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)  
In this work, we propose BarrierPoint, a sampling methodology to accelerate simulation by leveraging globally synchronizing barriers in multi-threaded applications.  ...  A number of sampling techniques have recently been developed that extend wellknown single-threaded techniques to allow sampled simulation of multi-threaded applications.  ...  Prior work [2] , [7] has shown that, as in single-threaded workloads, redundancy exists in the behavior of multi-threaded applications which allows detailed simulation of only part of the workload to  ... 
doi:10.1109/ispass.2014.6844456 dblp:conf/ispass/CarlsonHCE14 fatcat:kguga3khxjfbxnk56ygshkg65i

The Multi-Program Performance Model: Debunking current practice in multi-core simulation

Kenzo Van Craeynest, Lieven Eeckhout
2011 2011 IEEE International Symposium on Workload Characterization (IISWC)  
Given the very large number of possible multiprogram workloads and the limited speed of current simulation methods, it is impossible to evaluate all possible multi-program workloads.  ...  Because MPPM involves analytical modeling, it is very fast, and it estimates multi-core performance for a very large number of multi-program workloads in a reasonable amount of time.  ...  [18] propose the co-phase matrix as a method to quickly simulate multi-program workloads on multi-threaded architectures.  ... 
doi:10.1109/iiswc.2011.6114194 dblp:conf/iiswc/CraeynestE11 fatcat:vvnd5mwftzcxtbaoh77qc4z6ka

The benefit of SMT in the multi-core era

Stijn Eyerman, Lieven Eeckhout
2014 Proceedings of the 19th international conference on Architectural support for programming languages and operating systems - ASPLOS '14  
The number of active threads in a multi-core processor varies over time and is often much smaller than the number of supported hardware threads.  ...  The overall conclusion is that the benefit of SMT in the multi-core era is to provide flexibility with respect to the available thread-level parallelism.  ...  Stijn Eyerman is a postdoctoral fellow of the Research Foundation-Flanders.  ... 
doi:10.1145/2541940.2541954 dblp:conf/asplos/EyermanE14 fatcat:rnfzngcdang4xk5iaong2mz44y

Power profiling and optimization for heterogeneous multi-core systems

Kuen Hung Tsoi, Wayne Luk
2011 SIGARCH Computer Architecture News  
This paper presents a systematic approach for profiling the power and performance characteristics of application targeting heterogeneous multi-core computing platforms.  ...  Our approach enables rapid and automated design space exploration involving optimisation of workload distribution for systems with accelerators such as FPGAs and GPUs.  ...  The profiling experiment starts with a single thread and increases the number of threads until saturation. Figure 2 shows a common architecture for profiling multi-core FPGA design.  ... 
doi:10.1145/2082156.2082159 fatcat:o5cxa2rgjzdcnffu4aei7lqv4i

Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance

Rakesh Kumar, Dean M. Tullsen, Parthasarathy Ranganathan, Norman P. Jouppi, Keith I. Farkas
2004 SIGARCH Computer Architecture News  
This type of architecture covers a spectrum of workloads particularly well, providing high single-thread performance when thread parallelism is low, and high throughput when thread parallelism is high.  ...  A single-ISA heterogeneous multi-core architecture is a chip multiprocessor composed of cores of varying size, performance, and complexity.  ...  This research was funded in part by NSF grant CCR-0105743 and a grant from Intel Corporation.  ... 
doi:10.1145/1028176.1006707 fatcat:rzncce5rfrfevanucuc5uwkulu

Thread motion

Krishna K. Rangan, Gu-Yeon Wei, David Brooks
2009 SIGARCH Computer Architecture News  
Unfortunately, conventional DVFS, relying on off-chip regulators, faces limitations in terms of temporal granularity and high costs when considered for future multi-core systems.  ...  Thread motion extends workload-based power management into the nanosecond realm and, for a given power budget, provides up to 20% better performance than coarse-grained DVFS.  ...  Any opinions, findings, conclusions, or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the NSF.  ... 
doi:10.1145/1555815.1555793 fatcat:tyzheuc2sjci7awgi757gvuxli

Thread motion

Krishna K. Rangan, Gu-Yeon Wei, David Brooks
2009 Proceedings of the 36th annual international symposium on Computer architecture - ISCA '09  
Unfortunately, conventional DVFS, relying on off-chip regulators, faces limitations in terms of temporal granularity and high costs when considered for future multi-core systems.  ...  Thread motion extends workload-based power management into the nanosecond realm and, for a given power budget, provides up to 20% better performance than coarse-grained DVFS.  ...  Any opinions, findings, conclusions, or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the NSF.  ... 
doi:10.1145/1555754.1555793 dblp:conf/isca/RanganWB09 fatcat:kv3oif662bcdlbgz3kn2v7v5hu

Threads vs. caches: Modeling the behavior of parallel workloads

Zvika Guz, Oved Itzhak, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri C. Weiser
2010 2010 IEEE International Conference on Computer Design  
This paper provides a new model capturing the behavior of such parallel workloads on different multi-core architectures.  ...  Specifically, we provide a simple analytical model, which, for a given application, describes its performance and power as a function of the number of threads it runs in parallel, on a range of architectures  ...  Simulator We use an in-house simulator, MTM$im [21] , specifically designed for simulating graphics-oriented architectures with numerous cores.  ... 
doi:10.1109/iccd.2010.5647747 dblp:conf/iccd/GuzIKKMW10 fatcat:2x6ufha675cxhpwj5jo53d7xmu

Collecting signatures to model latency tolerance in high-level simulations of microthreaded cores

M. Irfan Uddin, Chris R. Jesshope, Michiel W. van Tol, Raphael Poss
2012 Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation Methods and Tools - RAPIDO '12  
We have developed a high-level simulator for the design space exploration of the Microgrid, which is a many-core architecture comprised of many finegrained multi-threaded cores.  ...  The previous method to evaluate the workload counted in basic blocks was inaccurate.  ...  Acknowledgement The author would like to acknowledge Andy Pimentel for feed back in this work.  ... 
doi:10.1145/2162131.2162132 dblp:conf/rapido/UddinJTP12 fatcat:ylakm5gbfngazf4ngr7jcy3dfe

Interval simulation: Raising the level of abstraction in architectural simulation

Davy Genbrugge, Stijn Eyerman, Lieven Eeckhout
2010 HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture  
Our experimental results using the SPEC CPU2000 and PARSEC benchmark suites and the M5 multi-core simulator, show good accuracy up to eight cores (average error of 4.6% and max error of 11% for the multi-threaded  ...  fullsystem workloads), while achieving a one order of magnitude simulation speedup compared to cycle-accurate simulation.  ...  Stijn Eyerman is a Postdoctoral Fellow with the Fund for Scientific Research in Flanders (Belgium) (FWO Vlaanderen).  ... 
doi:10.1109/hpca.2010.5416636 dblp:conf/hpca/GenbruggeEE10 fatcat:gjzjsmgz25ei7kd4sicd2v6vue

Core architecture optimization for heterogeneous chip multiprocessors

Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi
2006 Proceedings of the 15th international conference on Parallel architectures and compilation techniques - PACT '06  
Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core architectures for power and performance.  ...  The study is done for varying degrees of thread-level parallelism and for different area and power budgets.  ...  The research was funded in part by NSF grants CCF-0311683 and CCF-0541434, Semiconductor Research Corporation grant 2005-HJ-1313, and an IBM fellowship.  ... 
doi:10.1145/1152154.1152162 dblp:conf/IEEEpact/KumarTJ06 fatcat:nxca5scsdngpnkumwg74a4si6q

A novel power model for future heterogeneous 3D chip-multiprocessors in the dark silicon age

Arghavan Asad, Aniseh Dorostkar, Farah Mohammadi
2018 EURASIP Journal on Embedded Systems  
Comparisons show that the proposed model accurately estimates the power consumption of CMPs running both multi-threaded and multi-programed workloads.  ...  In the proposed architecture for future CMPs, we exploit emerging technologies such as non-volatile memories (NVMs) and 3D techniques to combat dark silicon.  ...  Publisher's Note Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.  ... 
doi:10.1186/s13639-018-0086-1 fatcat:3sjub2coxbhmhpuwhzrnaaggu4

A Grid Based Simulation Environment for Mobile Distributed Applications

Dawit Mengistu, Paul Davidsson, Lars Lundberg
2007 2007 International Conference on Multimedia and Ubiquitous Engineering (MUE'07)  
Since mobile devices can be modeled as autonomous intelligent agents, the multi agent based simulation (MABS) approach is useful for such applications.  ...  The findings of the experiment show that a Grid based MABS platform can provide a scalable simulation environment for mobile distributed applications.  ...  In this paper, we present a high level architecture of a dynamic simulation environment for MDC deployed on the Grid as a multi-agent based simulation (MABS) application.  ... 
doi:10.1109/mue.2007.16 dblp:conf/mue/MengistuDL07 fatcat:aifo62noyzfr3i457rgrpre4ni

Crossing the architectural barrier: Evaluating representative regions of parallel HPC applications

Alexandra Ferreoon, Radhika Jagtap, Sascha Bischoff, Roxana Rusitoru
2017 2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)  
However, as HPC systems reach exascale proportions, the cost of simulation increases, since simulators themselves are largely single-threaded.  ...  However, architectures new to HPC have a limited set of tools available.  ...  ACKNOWLEDGEMENTS The authors would like to thank Stephan Diestelhorst, Chris Adeniyi-Jones, Eric Van Hensbergen, Jonathan Beard and Charles García-Tobin for their feedback and support at the different stages of  ... 
doi:10.1109/ispass.2017.7975275 dblp:conf/ispass/FerreronJBR17 fatcat:5emsdpjxjvgbnhzwpt33mpkcnq
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