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Validating a Modern Microprocessor [chapter]

Bob Bentley
2005 Lecture Notes in Computer Science  
Introduction The microprocessor presents one of the most challenging design problems known to modern engineering.  ...  Future Challenges Validating the next generation of microprocessors is going to be a real challenge.  ... 
doi:10.1007/11513988_2 fatcat:po57mdscwjgavp6h6j4k7kadku

Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller

Michail Maniatakos, Naghmeh Karimi, Yiorgos Makris, Abhijit Jas, Chandra Tirumurti
2008 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems  
This paper presents a concurrent error detection technique for the control logic of a modern microprocessor.  ...  To evaluate the proposed method, we use a superscalar, dynamically-scheduled, out-of-order, Alpha-like microprocessor, on which we execute SPEC2000 integer benchmarks and we consider the coverage and the  ...  Acknowledgement This research was sponsored by a generous gift by Intel Corporation and was performed while the second author was a visiting student at Yale University. References  ... 
doi:10.1109/dft.2008.59 dblp:conf/dft/ManiatakosKMJT08 fatcat:mfooji2yezhs5op4vytnewl45m

PERFORMANCE OF AN ACTIVITY MONITOR INTEGRATED INTO A MICROPROCESSOR KNEE

Andy Sykes, Nadine Stech, Piotr Laszczak, Michael McGrath, Alan Kercher, Saeed Zahedi, David Moser
2018 Canadian Prosthetics & Orthotics Journal  
PERFORMANCE OF AN ACTIVITY MONITOR INTEGRATED INTO A MICROPROCESSOR KNEE.  ...  Modern microprocessor knees (MPKs) have begun to have this functionality built into the devices themselves, without the necessity for additional, external hardware.  ...  Modern microprocessor knees (MPKs) have begun to have this functionality built into the devices themselves, without the necessity for additional, external hardware.  ... 
doi:10.33137/cpoj.v1i2.32031 fatcat:j3mknducu5bg5mhg2fghf2oesi

Global Signal Vulnerability (GSV) Analysis for Selective State Element Hardening in Modern Microprocessors

Michail Maniatakos, Chandrasekharan Tirumurti, Rajesh Galivanche, Yiorgos Makris
2012 IEEE transactions on computers  
Experimentation with the Scheduler and Reorder Buffer modules of an Alpha-like microprocessor and a modern Intel microprocessor corroborates that GSV analysis generates a near-optimal ranking, yet is several  ...  Global Signal Vulnerability (GSV) analysis is a novel method for assessing the susceptibility of modern microprocessor state elements to failures in the field of operation.  ...  In this paper, we propose a new method for ranking state elements in modern microprocessors.  ... 
doi:10.1109/tc.2011.172 fatcat:6n2my6zva5fhjfofadxl7v4upq

Guest Editorial: Test and Verification Challenges for Future Microprocessors and SoC Designs

Sandip Ray, Jay Bhadra, Magdy S. Abadir, Li-C Wang
2013 Journal of electronic testing  
This has resulted in an increasing trend in design errors, manufacturing flaws, and security holes in modern VLSI systems.  ...  With increasing sophistication of VLSI technology, process, and architecture, microprocessors and SoC systems continue to increase in complexity.  ...  lenges and their synergy for modern and future VLSI systems.  ... 
doi:10.1007/s10836-013-5411-y fatcat:zfhwpkfkmfhivjtpsxsgu5wlry

An Efficient Low-Complexity Alternative to the ROB for Out-of-Order Retirement of Instructions

Salvador Petit, Rafael Ubal, Julio Sahuquillo, Pedro Lopez, Jose Duato
2009 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools  
Experimental results show that the VB microarchitecture is much more efficient than a ROB-based microprocessor.  ...  In this paper, a checkpoint-free out-of-order commit architecture is proposed, which replaces the ROB with a small structure called Validation Buffer (VB) from which instructions are retired as soon as  ...  Exploring the Behavior in a Modern Microprocessor This section explores the behavior of the VB microarchitecture while dimensioning the four major microprocessor structures closely resembling the ones  ... 
doi:10.1109/dsd.2009.237 dblp:conf/dsd/PetitUSLD09 fatcat:2v7xdzibdbbxxpzkf2whf4lmlu

Scalable hybrid verification of complex microprocessors

Maher Mneimneh, Fadi Aloul, Chris Weaver, Saugata Chatterjee, Karem Sakallah, Todd Austin
2001 Proceedings of the 38th conference on Design automation - DAC '01  
We introduce a new verification methodology for modern microprocessors that uses a simple checker processor to validate the execution of a companion high-performance processor.  ...  INTRODUCTION Modern microprocessors are enormously complex systems.  ...  In this paper, we present a new verification methodology that significantly lowers the burden of verifying modern microprocessor designs.  ... 
doi:10.1145/378239.378265 dblp:conf/dac/MneimnehAWCSA01 fatcat:qp2cnhdprvdadnlmkvrwzkzkzq

Guest Editorial

Prashant D. Joshi, Massimo Violante
2013 Journal of electronic testing  
The section entitled Analysis of faults and fault tolerant design for microprocessors and memories opens with Karimi et al. discussing the impact of performance faults in modern microprocessors; and continues  ...  low cost concurrent error detection strategy for the control logic of high performance microprocessors and its application to the instruction decoder.  ...  The section entitled Analysis of faults and fault tolerant design for microprocessors and memories opens with Karimi et al. discussing the impact of performance faults in modern microprocessors; and continues  ... 
doi:10.1007/s10836-013-5390-z fatcat:7lajb2lmxrdktckkzee3iz7c5i

Impact of modern memory subsystems on cache optimizations for stencil computations

Shoaib Kamil, Parry Husbands, Leonid Oliker, John Shalf, Katherine Yelick
2005 Proceedings of the 2005 workshop on Memory system performance - MSP '05  
Next we present a small parameterized probe and validate its use as a proxy for general stencil computations on three modern microprocessors.  ...  First we develop a simple benchmark to evaluate the effectiveness of prefetching in cache-based memory systems.  ...  Section 4 presents the Stencil Probe benchmark and validates its use as a proxy for general grid computations on three modern microprocessors.  ... 
doi:10.1145/1111583.1111589 dblp:conf/ACMmsp/KamilHOSY05 fatcat:ya5bhr22bjc3pjz6ox2rd2iotu

Vulnerability-based Interleaving for Multi-Bit Upset (MBU) protection in modern microprocessors

Michail Maniatakos, Maria K. Michael, Yiorgos Makris
2012 2012 IEEE International Test Conference  
We present a novel methodology for protecting incore microprocessor memory arrays from Multiple Bit Upsets (MBUs).  ...  Experimental results employing simulation of realistic MBU fault models on the instruction queue of the Alpha 21264 microprocessor in a 65nm process, demonstrate that a 30% selective parity protection  ...  and developing novel methods for protecting modern microprocessor core memory arrays against MBUs.  ... 
doi:10.1109/test.2012.6401594 dblp:conf/itc/ManiatakosMM12 fatcat:vyg2kstxtjd6vgciwpyofapule

Author Index

2021 2021 74th Conference for Protective Relay Engineers (CPRE)  
Modernization of an Industrial Power Distribution and Automation System -Validation Testing of IEC 61850 Process Bus Architecture in a Typical Digital Substation Lessons Learned Process Improvement of  ...  Vazquez PRACTICAL ASPECTS OF DESIGNING SAFE AND COMPACT MV SWITCHGEAR USING "AIR CORE CT", "RESISTOR VOLTAGE DIVIDER VT" AND MODERN INTELLIGENT MICROPROCESSOR RELAYS New Methods for Power Line Carrier  ... 
doi:10.1109/cpre48231.2021.9429846 fatcat:jeoj6nuzgrhlhcxdzztuzuzyky

On the Impact of Performance Faults in Modern Microprocessors

Naghmeh Karimi, Michail Maniatakos, Chandrasekharan Tirumurti, Yiorgos Makris
2013 Journal of electronic testing  
Modern microprocessors incorporate a variety of architectural features, such as branch prediction and speculative execution, which are not critical to the correctness of their operation yet are essential  ...  In this paper, we investigate quantitatively the performance impact of such faults using a superscalar, dynamically-scheduled, out-of-order, Alpha-like microprocessor, on which we execute SPEC2000 integer  ...  Acknowledgments This work is supported by a generous gift from Intel Corp. The first author performed this research while being a visiting student at Yale University.  ... 
doi:10.1007/s10836-013-5360-5 fatcat:teayxanktvcmxa2qqq77xv5l4e

Workload-Cognizant Concurrent Error Detection in the Scheduler of a Modern Microprocessor

Naghmeh Karimi, Michail Maniatakos, Abhijit Jas, Chandra Tirumurti, Yiorgos Makris
2011 IEEE transactions on computers  
We present a Concurrent Error Detection (CED) scheme for the Scheduler of a modern microprocessor.  ...  At a hardware cost of only 32 percent of the Scheduler, the corresponding CED scheme detects over 85 percent of its faults that affect the architectural state of the microprocessor.  ...  Modern microprocessors, for example, exhibit a high degree of application-level error masking.  ... 
doi:10.1109/tc.2010.265 fatcat:ruv5vlk6jbf3jluiplgznlzdke

Fabrication Attacks: Zero-Overhead Malicious Modifications Enabling Modern Microprocessor Privilege Escalation

Nektarios Georgios Tsoutsos, Michail Maniatakos
2014 IEEE Transactions on Emerging Topics in Computing  
As modern microprocessor chips are characterized by very dense, billion-transistor designs, such attacks must be very carefully crafted.  ...  The minimal footprint, however, comes at the cost of a small window of attack opportunities.  ...  The closest work to a modern microprocessor modification has been presented in [13] .  ... 
doi:10.1109/tetc.2013.2287186 fatcat:2ilqxrpczncfzhu5ekfvtxvsbe

Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study

Heon-Mo Koo, Prabhat Mishra, Jayanta Bhadra, Magdy Abadir
2006 Seventh International Workshop on Microprocessor Test and Verification (MTV'06)  
To address these challenges, we present a directed test generation technique at micro-architectural level for functional validation of microprocessors.  ...  Simulation-based validation of the current industrial proces sors typically use huge number of test programs generated at instruction set architecture (ISA) level.  ...  This paper presented a directed test generation technique based on decomposition of both processor model and properties for validation of performance as well as functionality of the modern microprocessors  ... 
doi:10.1109/mtv.2006.10 dblp:conf/mtv/KooMBA06 fatcat:4snlv6wvlrfmjhuhajmaazi5vu
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