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Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders

R. Dobkin, M. Peleg, R. Ginosar
2005 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
During 1997-2000, he worked within the RAFAEL ASIC Experts design group and during 2001-2002 led a very large-scale integration (VLSI) Design Group at IC4IC Ltd., developing family of chips for communications  ...  Standard VLSI implementations of turbo decoding require substantial memory and incur a long latency, which cannot be tolerated in some applications.  ...  ACKNOWLEDGMENT The authors are grateful to the anonymous referees for many helpful and constructive comments.  ... 
doi:10.1109/tvlsi.2004.842916 fatcat:rvh5lftc5vdanjiyvkti7r6ffu

Guest Editorial

Myung Hoon Sunwoo
2011 Journal of Signal Processing Systems  
The next two papers focus on the design of a Turbo decoder for multi-standards and a BCH decoder for 100Gb/s optical communications.  ...  These issues pose unprecedented challenges for the design and implementation of highly practical and reliable circuits and systems for broadband communications.  ...  The next two papers focus on the design of a Turbo decoder for multi-standards and a BCH decoder for 100Gb/s optical communications.  ... 
doi:10.1007/s11265-011-0632-8 fatcat:jnqvjozy6bhqddg56nyorf6ld4

A low power turbo/Viterbi decoder for 3GPP2 applications

Chien-Ching Lin, Y.-H. Shih, Hsie-Chia Chang, Chen-Yi Lee
2006 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
This paper presents a channel decoder that completes both turbo and Viterbi decodings, which are pervasive in many wireless communication systems, especially those that require very low signal-to-noise  ...  The measurement shows the power dissipation is 83 mW for the turbo decoding with six iterations at 3.1 Mb/s, and 25.1 mW for the Viterbi decoding at 1 Mb/s.  ...  ACKNOWLEDGMENT The authors would like to thank the National Chip Implementation Center for chip measurement assistance.  ... 
doi:10.1109/tvlsi.2006.874375 fatcat:mcvaybr5j5cs3ksangl43rhtpu

A Triple-Mode MAP/VA IP Design for Advanced Wireless Communication Systems

Cheng-hung Lin, Fan-min Li, Xin-yu Shi, An-yeu Wu
2005 2005 IEEE Asian Solid-State Circuits Conference  
For WCDMA standard, this IP can operate at clock frequency of 100 MHz and achieve throughput rate of 4.17Mbps@6 iterations for turbo decoding and 1.56Mbps for convolutional decoding in concurrent MAP/VA  ...  In this paper, a triple-Mode MAP/VA IP for advanced wireless communication Systems is implemented in 0.18µm CMOS process.  ...  VLSI ARCHITECTURE DESIGN To satisfy multiple advanced communication systems, a FEC engine (see Figure 1) , is necessary to change some control signal or memory bank for different systems.  ... 
doi:10.1109/asscc.2005.251705 fatcat:qejuta4o2zd5dezbvb3547ke3a

Editorial

An-Yeu (Andy) Wu, Ut-Va Koc, Keshab K. Parhi, Sergios Theodoridis
2003 EURASIP Journal on Advances in Signal Processing  
In the design and implementation domain of those systems, many research issues arise.  ...  Motivated by this design trend, the aim of this special issue is to present state-of-the-art signal processing techniques and implementation issues for broadband access systems over different access channels  ...  Chen et al. proposes a new signal security system and its VLSI architecture for real-time multimedia data transmission applications.  ... 
doi:10.1155/s1110865703002762 fatcat:2xhqalynvfhupodjnrmd757zg4

A 0.16nJ/bit/iteration 3.38mm2 turbo decoder chip for WiMAX/LTE standards

Cheng-Hung Lin, Chun-Yu Chen, En-Jui Chang, An-Yeu Wu
2011 2011 International Symposium on Integrated Circuits  
This paper presents a turbo decoder chip design supporting distinct convolutional turbo code schemes in WiMAX and LTE systems.  ...  Moreover, a warm-up free parallel MAP decoding is proposed to improve the throughput rate. The overall VLSI architecture of the proposed CTC decoder is presented for supporting the WiMAX/LTE systems.  ...  ACKNOWLEDGMENT The authors would like to thank Chip Implementation Center (CIC) for the support of chip fabrication and measurement.  ... 
doi:10.1109/isicir.2011.6131904 fatcat:wgu2rqoes5blddfomtpbkpccoa

Decoding in analog VLSI

H.-A. Loeliger, F. Tarkoy, F. Lustenberger, M. Helfenstein
1999 IEEE Communications Magazine  
This means that the design of such decoding networks in analog VLSI is similar in spirit to the design of digital networks with logic gates.  ...  CONCLUSIONS We have described recent research results on analog VLSI decoding networks for error correcting codes.  ... 
doi:10.1109/35.755457 fatcat:oakwfayq5refxkssfj7y5ni474

Guest editorial low power electronics and design

2001 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
L OW power design has played an important role in very large scale integration (VLSI ) design, particularly as we continue to double the number of transistors on a die every two years and increase the  ...  One important aspect of low power is mobile communications and its impact on our lives.  ...  He is involved in the design of architectures for wireless broad-band VLSI systems.  ... 
doi:10.1109/tvlsi.2001.920812 fatcat:xv2yzkxifzaalpkvzfqvneztli

FPGA REALIZATION OF SIMPLIFIED LTE TURBO DECODER

E Sujatha, C Subhas, M N Giri Prasad, N Padmaja
2021 INTERNATIONAL JOURNAL OF ELECTRICAL ENGINEERING & TECHNOLOGY  
The proposed design is synthesized and implemented on Zynq FPGA board.  ...  This work adopted Very large-scale Integration Optimization techniques of parallel computation, pipeline process for minimizing computation complexity and computation latency in each soft-input-softoutput  ...  Channel decoding is an ever interesting and challenging task for VLSI design engineers to implement its optimal system.  ... 
doi:10.34218/ijeet.12.9.2021.011 fatcat:wrm3vlacojh2dakp5jlp6wflhy

Equalization and FEC techniques for optical transceivers

K. Azadet, E.F. Haratsch, H. Kim, F. Saibi, J.H. Saunders, M. Shaffer, L. Song, Meng-Lin Yu
2002 IEEE Journal of Solid-State Circuits  
In this tutorial paper, we present the application of well-known DSP techniques used in lower speed wireline and wireless applications, to high-speed optical communications.  ...  generations Forward Error Correction (FEC), with special emphasis on VLSI implementation.  ...  Healey from Agere Systems for help with the fiber equalizer test setup and measurements.  ... 
doi:10.1109/4.987083 fatcat:xnispmebmfcvrpzrteiig7vjnm

A 640-Mb/s 2048-Bit Programmable LDPC Decoder Chip

M.M. Mansour, N.R. Shanbhag, M.M. Mansour, N.R. Shanbhag
2006 IEEE Journal of Solid-State Circuits  
The chip implements the turbo-decoding message-passing (TDMP) algorithm for architecture-aware (AA-)LDPC codes which has a faster convergence rate and hence a throughput advantage over the standard decoding  ...  The chip decodes any mix of 2048-bit rate-1/2 (3,6)-regular AA-LDPC codes in standard mode by programming the network, and attains a throughput of 640 Mb/s at 125 MHz for 10 TDMP-decoding iterations.  ...  Seok-Jun Lee for his assistance during the testing phase of the chip, and Dr. Makram M. Mansour for his support in building the parameterized leafcell layout library.  ... 
doi:10.1109/jssc.2005.864133 fatcat:osrslsl5zbeijmf24stbuibahm

Low Power Digital Multimedia Telecommunication Designs

Koon-Shik Cho, Jun-Dong Cho
2001 VLSI design (Print)  
The increasing prominence of wireless multimedia systems and the need to limit power capability in very-high density VLSI chips have led to rapid and innovative developments in low-power design.  ...  Power reduction has emerged as a significant design constraint in VLSI design. The need for wireless multimedia systems leads to much higher power consumption than traditional portable applications.  ...  The low-power technique designs these systems requires vertical integration of the design process at all levels, from algorithm development to system architecture to circuit layout.  ... 
doi:10.1155/2001/43078 fatcat:rhrxisx42vcc5e4uohkpefdq7m

Guest Editorial Special Section on Application Specific Processors

Paolo Ienne, Peter Petrov
2008 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
With the current numbers of transistors available on typical VLSI dies, processors are rapidly becoming the keystone of system design: single chips may contain several of them, ranging from extremely simple  ...  He has served as a technical program member of the Symposium on Integrated Circuits and Systems (SBCCI) and the International Conference on Computer Design (ICCD).  ... 
doi:10.1109/tvlsi.2008.2005245 fatcat:jqbqopqzovamzbmvfcmr3tyl5u

Table of contents

2020 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Pavlidis 2551 Design of SEU-Tolerant Turbo Decoders Implemented on SRAM-FPGAs .................................................. ................................................................. Z.  ...  Joler 2540 Coding Circuits Energy-Efficient Time-Based Adaptive Encoding for Off-Chip Communication ............................................ ........................................................  ... 
doi:10.1109/tvlsi.2020.3038499 fatcat:rrnerogusremlfecnw7b57uoya

Binary de Bruijn interconnection network for a flexible LDPC/turbo decoder

Hazem Moussa, Amer Baghdadi, Michel Jezequel
2008 2008 IEEE International Symposium on Circuits and Systems  
The flexibility and the scalability of this on-chip communication network enable it to be used in the emerging multi-code applications and standards.  ...  This paper proposes a novel on-chip interconnection network adapted to a flexible multiprocessor LDPC/turbo decoder and based on the de Bruijn network.  ...  ON-CHIP COMMUNICATION NETWORK Figure 1.  ... 
doi:10.1109/iscas.2008.4541363 dblp:conf/iscas/MoussaBJ08 fatcat:iyj26aymargtznrhu4vopn5ugq
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