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General-purpose systolic arrays

K.T. Johnson, A.R. Hurson, B. Shirazi
1993 Computer  
Behrooz Shirazi, University of Texas, Arlington Systolic arrays effectively exploit massive parallelism in computationally intensive applications.  ...  With advances in VLSI, WSI, and FPGA technologies, they have progressed from fixedfunction to generalpurpose architectures. hen Sun Microsystems introduced its first workstation, the company could not  ...  While systolic arrays originally were used for fixed or special-purpose architectures, the systolic concept has be en extend e d t o genera 1 -purpose SIMD and MIMD architectures.  ... 
doi:10.1109/2.241423 fatcat:5pbdb7wypbbqzk7riagtv5jsvq

Compiler optimizations for asynchronous systolic array programs

M. Lam
1988 Proceedings of the 15th ACM SIGPLAN-SIGACT symposium on Principles of programming languages - POPL '88  
This asynchronous communication model is recommended even for programming algorithms on systolic arrays without dynamic flow control between cells.  ...  The ideas presented in the paper have been validated in the compiler for the Warp machine [4] .  ...  Kung, for his support and advice in the past many years. I would like to thank all the members in the Warp project, and in particular, Thomas Gross for his effort in the W2 compiler.  ... 
doi:10.1145/73560.73587 dblp:conf/popl/Lam88 fatcat:xh773asr2jbsnnit4nrnmymzdq

The UCSC Kestrel Application-Unspecific Processor

Richard Hughey, Andrea Blas
2006 IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06)  
Experience with Kestrel indicates that programmable systolic processing, and its natural combination with the Single Instruction-Multiple Data (SIMD) parallel architecture, will be an effective design  ...  Kestrel combines an ALU, multiplier, and local memory, with Systolic Shared Registers for seamless merging of communication and computation, and an innovative condition stack for rapid conditionals.  ...  The second wave included the use of single-chip (MIC-SMACS) or single-board (Warp) processors to create short systolic arrays designed for signal processing but suitable for sequence analysis and other  ... 
doi:10.1109/asap.2006.66 dblp:conf/asap/HugheyB06 fatcat:zl7dyipt6zaktbxr4tkrs3wuxq

Embedded Parallel Systolic architecture for multi-filtering techniques using FPGA

Muataz H. Salih, M. R. Arshad
2010 2010 2nd International Conference on Electronic Computer Technology  
This new architecture design called Embedded Parallel Systolic Filters (EPSF) that can process data gathered from sensors and landmarks are proposed in our study using a high-density reconfigurable device  ...  Keywords-embedded system design; FPGA system design; systolic architecture; underwater detection I.  ...  ACKNOWLEDGMENT The authors would like to thank the Underwater Robotics Research Group (URRG) in USM for their assistance and MOSTI for providing the research grant (grant no. 605124).  ... 
doi:10.1109/icectech.2010.5479973 fatcat:ibvimtetszaa3bn7hiwnk34e7a

The Warp Computer: Architecture, Implementation, and Performance

Marco Annaratone, Emmanuel Arnould, Thomas Gross, H. T. Kung, Monica Lam, Onat Menzilcioglu, Jon A. Webb
1987 IEEE transactions on computers  
The revision also incorporated several T HE Warp machine is a high-performance systolic array architectural improvements.  ...  For these applications, Warp is 1986, these two prototype machines were used on a daily basis typically several hundred times faster than a VAX 11/780 class at Carnegie Mellon. computer.  ...  using a laser range-finder, and path 3) Pipelining: In this model, typical of systolic computa-planning using dynamic programming.  ... 
doi:10.1109/tc.1987.5009502 fatcat:xup2rwwivjb2jfjnb3fhiwgv7i

Warp architecture and implementation

M. Annaratone, E. Arnould, T. Gross, H. T. Kung, M. S. Lam
1986 SIGARCH Computer Architecture News  
A high-performance systolic array computer called Warp has been designed and constructed.  ...  This paper describes the architecture and implementation of the Warp machine, and justifies and evaluates some of the architectural features with system, software and application considerations 0884-7495  ...  In particular, a single Warp cell can be time multiplexed to perform the function of a column of cells, and therefore the linear array can, for example, implement a two-dimensional systolic array effectively  ... 
doi:10.1145/17356.17397 fatcat:abfuba7b4zcutn34kvwfwhlbie

Computational Models for Parallel Computers

H. T. Kung
1988 Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences  
Emphases are placed upon models for one-dimensional processor arrays, reflecting Carnegie Mellon's experiences with the Warp systolic array machine.  ...  They can be used to derive the architecture of the machine, provide guidelines for programming tools, and suggest how the machine should be used in applications.  ...  Webb, for their implementation of some of the applications examples discussed in this paper.  ... 
doi:10.1098/rsta.1988.0092 fatcat:zu6onbmdcbfgxewi5fosgwgcz4

Finding the Next Computational Model: Experience with the UCSC Kestrel

Richard Hughey, Andrea Di Blas
2007 Journal of Signal Processing Systems  
The second wave included the use of single-chip (MICSMACS) or single-board (Warp) processors to create short systolic arrays designed for signal processing but suitable for sequence analysis and other  ...  This wave also saw the development of P-NAC's successor, the Brown Systolic Array (B-SYS, 47 PEs/chip).  ...  Acknowledgements The authors thank the many contributors to the hardware, software, and algorithms of the The authors also thank the National Science Foundation, Affymax, and the University of California for  ... 
doi:10.1007/s11265-007-0130-1 fatcat:wdghbbthsnae7hzoecump77omy

Computer-aided modeling and evaluation of reconfigurable VLSI processor arrays with VHDL

Kuochen Wang, Sy-Yen Kuo
1992 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
The results from this research can drive the applications of large-area VLSI or WSI (wafer scale integration) closer to reality and result in low-cost, high-yield array architectures.  ...  In this paper, we present an integrated computeraided design environment, the VAR (VHDL-based Array Reconfiguration) system, for the tasks of design, reconfiguration, simulation, and evaluation in an architecture  ...  MODELING DEFECT-TOLERANT ARRAY USING VHDL A systolic array will be used as an example to illustrate the modeling process for defect-tolerant arrays using VHDL.  ... 
doi:10.1109/43.124397 fatcat:r2f2xugh6zh2tnb7vlhgi2njgu

A flexible architecture for image processing

R.W Hartenstein, A Hirschbiel, M Weber
1987 Microprocessing and Microprogramming  
Keywords: ¥ image processing¥ flexible architecture ¥ pattern matching, recognition¥ segmentation, shrink,expand ¥ VLSI layout processing¥ routing -VLSI impact on architectures -Tools and methods for architecture  ...  design and description -computer architecture -Map oriented data processing ABSTRACT The paper describes an innovative computation resource concept which for a class of data processing problems is an  ...  In the latter application MOM would be used as a CAD tool (like a programmable systolic array compiler, or a systolic array compiler) within a toolbox for the design of systolic architectures.  ... 
doi:10.1016/0165-6074(87)90019-6 fatcat:yn6nb2ctqbgvdgbylk4wocu7y4

Why systolic architectures?

Kung
1982 Computer  
0 This article reviews the basic principle of systolic architectures and explains why they should result in cost-effective, highperformance special-purpose systems for a wide range of problems.  ...  We intend to help correct this ad hoc approach by providing a general guideline-specifically, the concept of systolic architecture, a general methodology for mapping high-level computations into hardware  ...  COMPUTER 38 Systolic architectures: the basic principle As a solution to the above challenges, we introduce systolic architectures, an architectural concept originally proposed for VLSI implementation  ... 
doi:10.1109/mc.1982.1653825 fatcat:7ciz7pfl7fdcra4ljse4p3raju

Experience With The CMU Programmable Systolic Chip

Allan L. Fisher, H. T. Kung, Kenneth Sarocky, Keith Bromley
1984 Real-Time Signal Processing VII  
Hsu wrote the PSC image processing code for the demonstration system. Some chip testing software was developed by Monica Lam.  ...  Acknp*vlpdgmeirt5 The PSC is a result of a team effort; its architecture and design have been reported in separate papers, 2,3 ' 4 on which some of the material of this paper is based. F. H.  ...  This concern is especially significant for systolic arrays, as their performance relies on the use of large numbers of cells in the array.  ... 
doi:10.1117/12.944017 fatcat:mmkb54l5encxzobk7cwaoh3yq4

VLSI Architecture for Real-Time HD1080p View Synthesis Engine

Ying-Rung Horng, Yu-Cheng Tseng, Tian-Sheuan Chang
2011 IEEE transactions on circuits and systems for video technology (Print)  
For the memory cost, we propose the frame-level pipelining to reduce the requirement of warped depth maps, and the column-order warping method to remove the Z-buffer in occlusion handling.  ...  Index Terms-3-D video coding, view synthesis, VLSI design.  ...  A general method is matrix decomposition, such as singular value decomposition, which can be accelerated by the systolic array architecture [26] and the processor-based architecture, called coordinate  ... 
doi:10.1109/tcsvt.2011.2148410 fatcat:mbjlgopnnvfyxka2deucjqfmou

Parallel system design for time-delay neural networks

D. Zhang, S.K. Pal
2000 IEEE Transactions on Systems Man and Cybernetics Part C (Applications and Reviews)  
In this paper, we develop a parallel structure for the time-delay neural network used in some speech recognition applications.  ...  The effectiveness of the design is illustrated by 1) extracting a window computing model from the time-delay neural systems; 2) building its pipelined architecture with parallel or serial processing stages  ...  Kamel of the University of Waterloo for their valuable help.  ... 
doi:10.1109/5326.868447 fatcat:yyrza3zrojhmfoydtjwnamseci

Supporting systolic and memory communication in iWarp

Shekhar Borkar, Craig Peterson, Jim Susman, Jim Sutton, John Urbanski, Jon Webb, Robert Cohn, George Cox, Thomas Gross, H. T. Kung, Monica Lam, Margie Levine (+2 others)
1990 Proceedings of the 17th annual international symposium on Computer Architecture - ISCA '90  
A resident run-time system on each cell supports systolic and memory communication.  ...  This paper complements earlier iWarp papers on other topics: iWarp overview [5], architecture and compiler tradeoffs for the computation agent [6] . and networks that can be formed on an iWarp array [9  ...  We also thank Abu Noamsn and David Yam of Carnegie Mellon University for assistance in design validation and performance evaluation.  ... 
doi:10.1145/325164.325116 dblp:conf/isca/BorkarCCGKLLMMPSSUW90 fatcat:u34kdq5fdjei5ngq4vop4h34hq
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