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Netlist and System Partitioning [chapter]

Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
2011 VLSI Physical Design: From Graph Partitioning to Timing Closure  
make things easy, groups of tightly-connected nodes can be clustered, absorbing connections between these nodes Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning  ...  Given: A graph with 2n nodes where each node has the same weight. Goal: A partition (division) of the graph into two disjoint subsets A and B with minimum cut cost and |A| = |B| = n.  ... 
doi:10.1007/978-90-481-9591-6_2 fatcat:nn274cy5tjhjtm23lwnetgln6m

Global and Detailed Placement [chapter]

Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
2011 VLSI Physical Design: From Graph Partitioning to Timing Closure  
of a placement • Static timing analysis using actual arrival time (AAT) and required arrival time (RAT) − AAT(v) represents the latest transition time at a given node v measured from the beginning of  ...  cross e, making P more likely to be unroutable. • The wire density of P is where E is the set of all edges • If Φ(P) ≤ 1, then the design is estimated to be fully routable, otherwise routing will need  ...  Power Rail Standard Cell Row • Extensions to optimize routed wirelength, routing congestion and circuit timing • Relatively straightforward algorithms, but high-quality, fast implementation is important  ... 
doi:10.1007/978-90-481-9591-6_4 fatcat:cupczcuqkzfxrawioqf2rqm5hq

Design topology aware physical metrics for placement analysis

Shyam Ramji, Nagu R. Dhanwada
2003 Proceedings of the 13th ACM Great Lakes Symposium on VLSI - GLSVLSI '03  
timing closure.  ...  However, the actual timing measure, which is used in a design closure loop, is path-based and dependent on the network topology.  ...  The timing measures reported in the table corresponds to the design state before physical synthesis phase in the design closure flow (figure 1).  ... 
doi:10.1145/764808.764857 dblp:conf/glvlsi/RamjiD03 fatcat:lmwhryl2rzcw5nwqbqu4ilodu4

Design topology aware physical metrics for placement analysis

Shyam Ramji, Nagu R. Dhanwada
2003 Proceedings of the 13th ACM Great Lakes Symposium on VLSI - GLSVLSI '03  
timing closure.  ...  However, the actual timing measure, which is used in a design closure loop, is path-based and dependent on the network topology.  ...  The timing measures reported in the table corresponds to the design state before physical synthesis phase in the design closure flow (figure 1).  ... 
doi:10.1145/764856.764857 fatcat:mtkin2mku5h4rl6yl7rxajnqdy

A distributed VLSI architecture for efficient signal and data processing

Jean-Luc Gaudiot, Rex W. Vedder, George K. Tucker, Dennis Finn, Michael L. Campbell
1985 IEEE transactions on computers  
The processing elements have been designed so as to re duce the number of VLSI component types required and for modularity of the physical system.  ...  The model of execution derived from original data-flow principles is presented as well as the different soft ware tools which give the system its high-level language programmability (compiler, allocator  ...  Most of this time is spent computing the transitive closure of the graph.  ... 
doi:10.1109/tc.1985.6312207 fatcat:eetap5trdjbz5fayd5ifwye6w4

Survey of Machine Learning for Electronic Design Automation

Kevin Immanuel Gubbi, Sayed Aresh Beheshti-Shirazi, Tyler Sheaves, Soheil Salehi, Sai Manoj PD, Setareh Rafatirad, Avesta Sasan, Houman Homayoun
2022 Proceedings of the Great Lakes Symposium on VLSI 2022  
They are utilized in Synthesis, Physical Design (Floorplanning, Placement, Clock Tree Synthesis, Routing), IR drop analysis, Static Timing Analysis (STA), Design for Test (DFT), Power Delivery Network  ...  State-of-the-art ML-based VLSI-CAD tools, current trends, and future perspectives of ML in VLSI-CAD are also discussed. CCS CONCEPTS • Hardware → Design databases for EDA.  ...  To do so, LSOracle applies k-way partitioning to split a Directed Acyclic Graph (DAG) into multiple partitions and chooses the best-fit optimizer.  ... 
doi:10.1145/3526241.3530834 fatcat:zixyjpof45b25kvlootimwrusu

A Reinforcement Learning-Based Framework to Generate Routing Solutions and Correct Violations in VLSI Physical Design [article]

Upma Gandhi, University Of Calgary, Laleh Behjat
2020
Routing is one of the most difficult and time-consuming parts of physical design, where over a million connections have to be routed in a 3D arrangement while following strict design and manufacturing  ...  The process of making an IC is called Very Large Scale Integration (VLSI). Under this process, a physical design step takes place in which the physical shapes of circuit elements are determined.  ...  . • Timing closure The Timing closure process is an optimization step of the VLSI physical design that governs the application of timings constraints of IC layout after the routing step [4] [36] .  ... 
doi:10.11575/prism/37475 fatcat:33qmufwl5neo5ft2ljxsf6jksq

A Comparative Study of VLSI 3D Placement for power management and wirelength reduction

T. Kapilachander, B. Vijayashree, E. Rajthilak
2018 International Journal of Engineering Research and  
In recent days every application must need power management and area management such physical problems and aspects of VLSI design.  ...  Three-dimensional (3D) integration is a viable approach that allows designers to add functionality to the devices while maintaining the same die area without the need for new design process.  ...  can choose from a wide range of options for reduction in power consumption of VLSI circuits.  ... 
doi:10.17577/ijertcon052 fatcat:y4qeppfoqzhephtkwt66dqlzue

Area-time complexity for VLSI

C. D. Thompson
1979 Proceedings of the eleventh annual ACM symposium on Theory of computing - STOC '79  
495 The complexity of the Discrete Fourier Transform (OFT) is studied with respect to a new model of computation appropriate to VLSI technology.  ...  Lower bounds on area (A) and time (T) are related to the number of points (N) in the OFT: AT2 > N2/16.  ...  Theorem 2: Associate a graph with each VLSI design as in Section 4. At least N/(2w) time is required to compute an N point OFT on a VLSI design that corresponds to a graph of width w. Proof sketch.  ... 
doi:10.1145/800135.804401 dblp:conf/stoc/Thompson79 fatcat:pkzhvy6w6bh6biqcrxrfl35iou

A Study of Floorplanning Challenges and Analysis of macro placement approaches in Physical Aware Synthesis

Shivani Garg, Neeraj Kr. Shukla
2016 International Journal of Hybrid Information Technology  
Now, physical aware synthesis gives a user an opportunity to cut the implementation time at later stages.  ...  Thus we can easily automate floorplanning for different shapes of die and reduce cycle time from months to few weeks.  ...  The floorplanning affects the design cycle time in entire design flow from design planning to implementation. [6] .  ... 
doi:10.14257/ijhit.2016.9.1.24 fatcat:7ctrofrlnvbl3gio72e7zju2je

Shift Left Trends for Design Convergence in SOC: An EDA Perspective

Vivek Bhardwaj
2021 International Journal of Computer Applications  
, power, software tools, turnaround time  ...  Design convergence of System on Chips has become a major problem to solve in semiconductor industry.  ...  At the time when timing the design through STA(Static Timing Analysis) was decoupled from the key physical steps, designers often found surprises and found it very difficult to close timing progressively  ... 
doi:10.5120/ijca2021921053 fatcat:r4om4icdrve4xczxa7vjx6z2i4

Clock-Latency-Aware Pre-CTS for better Timing Closure in VLSI Design

Jalal Benallal, Sultan Moulay Slimane University, Med V Av, B.P 591, Béni Mellal, Morocco, Abdellah Bouamama, Lekbir Cherif, Mohammed Darmi, Rachid Elgouri, Nabil Hmina
2022 International Journal of Emerging Technology and Advanced Engineering  
Keywords—Clock-latency estimation, Clock-tree Synthesis, Integrated circuit conception, Physical implementation, Static timing analysis, Static timing closure.  ...  As a result, the transition from the pre-CTS stage to the post-CTS stage becomes easier without significant timing jumps.  ...  INTRODUCTION Achieving high performance with new very large-scale integration (VLSI) designs is a complicated and delicate task.  ... 
doi:10.46338/ijetae0222_10 fatcat:6ym6d2dmbfbvhdyynrvoofkw6a

Arbitrarily shaped rectilinear module placement using the transitive closure graph representation

Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang
2002 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
In this paper, we deal with arbitrarily shaped rectilinear module placement using the transitive closure graph (TCG) representation.  ...  We first partition a rectilinear module into a set of submodules and then derive necessary and sufficient conditions of feasible TCG for the submodules.  ...  To move a reduction edge from a transitive closure graph to the other in a TCG, we first delete from and then add to .  ... 
doi:10.1109/tvlsi.2002.808431 fatcat:dqhygxbflne6rpyl2ogtc5pxz4

Manufacturability Aware Routing in Nanometer VLSI

David Z. Pan
2010 Foundations and Trends® in Electronic Design Automation  
Thus, the conventional design "closure" (on timing/noise, etc.) may not automatically guarantee the manufacturing closure due to the manufacturing yield loss.  ...  For difficult designs, these steps may need to be repeated in order to satisfy multiple design constraints (e.g., timing, power, noise, and so on) and reach the design closure.  ... 
doi:10.1561/1000000015 fatcat:ytvthtu4b5hwzdume5ffs4yxpe

Concurrent CPU-GPU Task Programming using Modern C++ [article]

Tsung-Wei Huang, Yibo Lin
2022 arXiv   pre-print
In this paper, we introduce Heteroflow, a new C++ library to help developers quickly write parallel CPU-GPU programs using task dependency graphs.  ...  We have evaluated Heteroflow on two real applications in VLSI design automation and demonstrated the performance scalability across different CPU-GPU numbers and problem sizes.  ...  VLSI Placement We applied Heteroflow to solve a VLSI placement problem, a fundamental step in the physical design stage (see Figure 2 ).  ... 
arXiv:2203.08395v1 fatcat:rff642orzrff3k56rofcbux3ve
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