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Design and implementation of a private and public key crypto processor and its application to a security system

Ho Won Kim, Sunggu Lee
2004 IEEE transactions on consumer electronics  
The crypto processor consists of a 32-bit RISC processor block and coprocessor blocks dedicated to the AES, KASUMI, SEED, triple-DES private key crypto algorithms and ECC and RSA public key crypto algorithm  ...  The crypto processor has been designed and implemented using an FPGA, and some parts of crypto algorithms have been fabricated as a single VLSI chip using 0.5 m µ CMOS technology.  ...  CONCLUSIONS AND FUTURE WORKS In this paper, we have presented the design and implementation of a crypto processor composed of a 32-bit RISC processor and coprocessor blocks dedicated to the AES, KASUMI  ... 
doi:10.1109/tce.2004.1277865 fatcat:xoa5gsqctrakdmenyhxakrx5ma

A Flexible Crypto-system Based upon the REDEFINE Polymorphic ASIC Architecture

Ganesh Garga, Saptarsi Das, S. Nandy, Ranjani Narayan, Chandan Haldar, Maheshkumar Jagtap, Siba Dash
2012 Defence Science Journal  
As another point of comparison, the OpenSSl implementation of the ECC operation (random base point) achieves around 350 operations/ second on a 450 MHz UltraSPARC 2 processor 14 .  ...  When designing a flexible cryptosystem, the challenge is to make use of some of the hardware resources dedicated to obtain a high performance AES implementation, in order to accelerate other cryptographic  ... 
doi:10.14429/dsj.62.1438 fatcat:m6uifzj7ejg33bujviajwstvtq

Reconfigurable Architecture for Elliptic Curve Cryptography Using FPGA

A. Kaleel Rahuman, G. Athisha
2013 Mathematical Problems in Engineering  
The hardware design is based on optimized finite state machine (FSM), with a single cycle 193 bits multiplier, field adder, and field squarer.  ...  The different optimization at the hardware level improves the acceleration of the ECC scalar multiplication, increases frequency and the speed of operation such as key generation, encryption, and decryption  ...  The proposed architecture has the feature of modularity and a simple control structure; it is well suited to VLSI implementations (see Algorithm 1) .  ... 
doi:10.1155/2013/675161 fatcat:rvpqoytb3fedtlfveiicokyn4i

The design space of ultra-low energy asymmetric cryptography

Andrew D. Targhetta, Donald E. Owen, Paul V. Gratz
2014 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)  
Next, we introduce a reconfigurable GF (p) accelerator to our microarchitecture and meaii  ...  Thus, we implement a parameterizable instruction cache and simulate various configurations.  ...  Without their invaluable guidance and efforts, none of this work would have been possible.  ... 
doi:10.1109/ispass.2014.6844461 dblp:conf/ispass/TarghettaOG14 fatcat:ghiu2f6srfe5temv2tft7ywkqu

Memory-based computing for performance and energy improvement in multicore architectures

Kamran Rahmani, Prabhat Mishra, Swarup Bhunia
2012 Proceedings of the great lakes symposium on VLSI - GLSVLSI '12  
Experimental results demonstrate that on-demand memory-based computing in each core can significantly improve performance (up to 4.7X, 3.3X on average) as well as reduce energy consumption (up to 4.7X,  ...  Memory-based computing (MBC) is promising for improving performance and energy efficiency in both data-and compute-intensive applications.  ...  scenario functional unit in multicore systems to provide hardware acceleration.  ... 
doi:10.1145/2206781.2206851 dblp:conf/glvlsi/RahmaniMB12 fatcat:4vs5sirdwvhllhpwxvthh5uzhi

IMCRYPTO: An In-Memory Computing Fabric for AES Encryption and Decryption [article]

Dayane Reis, Haoran Geng, Michael Niemier, Xiaobo Sharon Hu
2021 arXiv   pre-print
IMCRYPTO employs a unified structure to implement encryption and decryption in a single hardware architecture, with combined (Inv)SubBytes and (Inv)MixColumns steps.  ...  This paper proposes IMCRYPTO, an in-memory computing (IMC) fabric for accelerating AES encryption and decryption.  ...  Amplifiers (3) Key and 1 piece of data (4 registers of 32 bits each).  ... 
arXiv:2112.02231v1 fatcat:syl43abzgndqzmxoxboqppepke

Quick Boot of Trusted Execution Environment with Hardware Accelerators

Trong-Thuc Hoang, Ckristian Duran, Duc-Thinh Nguyen-Hoang, Duc-Hung Le, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham
2020 IEEE Access  
TileLink is used for the communications between the processor and the register of the accelerators. For the TEE boot, the software procedures are switched with the accelerated counterpart.  ...  Comparing to the software approach, a 2.5-decade increment is observed in the throughput of the signature procedure using the SHA-3 acceleration for big chunks of data.  ...  This TPM implements standard security algorithms and crypto-primitives like SHA-1, SHA-256, RSA, ECC, AES-128, HMAC, and MGF1 for trusted computing [23] , [24] .  ... 
doi:10.1109/access.2020.2987617 fatcat:suwt3w22j5dfbifiau7fs5bdfy

2021 Index IEEE Transactions on Very Large Scale Integration (VLSI) Systems Vol. 29

2021 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
The primary entry includes the coauthors' names, the title of the paper or other item, and its location, specified by the publication abbreviation, year, month, and inclusive pagination.  ...  Departments and other items may also be covered if they have been judged to have archival value. The Author Index contains the primary entry for each item, listed under the first author's name.  ...  Aljuffri, A., +, TVLSI Nov. 2021 1930-1942 Area-Efficient Nano-AES Implementation for Internet-of-Things Devices.  ... 
doi:10.1109/tvlsi.2021.3136367 fatcat:fwqswbyzejgfhgbzywrvsf2qgi

SRAM-SUC: Ultra-Low Latency Robust Digital PUF [article]

Ayoub Mars, Hussam Ghandour, Wael Adi
2021 arXiv   pre-print
Hardware and software implementations show that the resulting SRAM-SUC has ultra-low latency compared to well-known PUF-based authentication mechanisms.  ...  This work also presents a class of involutive SUCs, optimized for the targeted SoC FPGA architecture, as sample realization of the concept; it deploys a generated class of involutive 8-bit S-Boxes, that  ...  Each unit cell consists of a 2-input XOR gate where one of its inputs is connected to an input key bit and the other is connected to the strongly skewed-1 latch, which is connected to a virtual connection  ... 
arXiv:2106.07105v1 fatcat:aq5hshyj4nfu7eyxfxj4ml74sm

The M2DC Project: Modular Microserver DataCentre

Mariano Cecowski, Giovanni Agosta, Ariel Oleksiak, Michal Kierzynka, Micha vor dem Berge, Wolfgang Christmann, Stefan Krupop, Mario Porrmann, Jens Hagemeyer, Rene Griessl, Meysam Peykanu, Lennart Tigges (+13 others)
2016 2016 Euromicro Conference on Digital System Design (DSD)  
This paper provides an overview of the different topics FPGAs have been used for in the last 15 years of research and why they have been chosen over other processing units like e.g. CPUs.  ...  Since their introduction, FPGAs can be seen in more and more different fields of applications.  ...  inputs of a processing unit and reacts to the unit's outgoing signals. 11) Prototyping: One of the main application fields for FPGAs right from the start of their usage has been the functional prototyping  ... 
doi:10.1109/dsd.2016.76 dblp:conf/dsd/CecowskiAOKBCKP16 fatcat:bu4nbkqaejebjafrotibui6mkq

Field Programmable Gate Array Applications—A Scientometric Review

Juan Ruiz-Rosero, Gustavo Ramirez-Gonzalez, Rahul Khanna
2019 Computation  
Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science).  ...  Also, we present an evolution and trend analysis of the related applications.  ...  Electromagnetic Transient Faults Injection on a hardware and a software implementations of AES.  ... 
doi:10.3390/computation7040063 fatcat:wxtatzsvvnfopghdfl25hcfc2a

AxRLWE: A Multilevel Approximate Ring-LWE Co-Processor for Lightweight IoT Applications

Dur-E-Shahwar Kundi, Ayesha Khalid, Song Bian, Chenghua Wang, Maire O'Neill, Weiqiang Liu
2022 IEEE Internet of Things Journal  
With 45nm CMOS technology, AxRLWE was bench-marked to fit well within the same area-budget of lightweight ECC processor and consume a third of energy compared to special class of R-Binary LWE (R-BLWE)  ...  Undertaking AxRLWE on Field Programmable Gate Arrays (FPGAs), we bench-marked a 64% area reduction cost compared to earlier accurate R-LWE designs at the cost of reduced quantum-security.  ...  ACKNOWLEDGEMENT This work is supported by grants from the National Natural Science Foundation of China (62022041 and 61871216) and the Engineering and Physical Sciences Research Council of U.K.  ... 
doi:10.1109/jiot.2021.3122276 fatcat:tdufb6w6vrgcfaopsvxqmdzwp4

Efficient FPGA-based ECDSA Verification Engine for Permissioned Blockchains [article]

Rashmi Agrawal, Ji Yang, Haris Javaid
2021 arXiv   pre-print
From our implementation on Xilinx Alveo U250 accelerator board with target frequency of 250MHz, our ECDSA verification engine can perform a single verification in 760μ s resulting in a throughput of 1,315  ...  In this paper, we propose an efficient implementation of ECDSA signature verification on an FPGA, in order to improve the performance of permissioned blockchains that aim to use FPGA-based hardware accelerators  ...  verification unit on a Xilinx XC5VLX110T Virtex-5 FPGA.  ... 
arXiv:2112.02229v1 fatcat:r3bw4kn4tnhzvhh3cjqugnj65m

2020 Index IEEE Transactions on Very Large Scale Integration (VLSI) Systems Vol. 28

2020 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
., Conflux-An Asynchronous Two-to-One Multiplexor for Time-Division Multiplexing and Clockless, Tokenless Readout; TVLSI Feb. 2020 503-515 Holcomb, D., see 2685-2698 Holcomb, D.E., see 1807-1820 Homayoun  ...  Reconfigurable Power-Efficient Ternary Content-Addressable Memory on FPGAs; TVLSI Aug. 2020 Aug. 1925Aug  ...  ., +, TVLSI Jan. 2020 174-187 Boolean functions A VLSI Majority-Logic Device Based on Spin Transfer Torque Mechanism for Brain-Inspired Computing Architecture.  ... 
doi:10.1109/tvlsi.2020.3041879 fatcat:33vb2eia2jfjpog4wei4peq5ge

Hardware/Software Adaptive Cryptographic Acceleration for Big Data Processing

Chunhua Xiao, Lei Zhang, Yuhua Xie, Weichen Liu, Duo Liu
2018 Security and Communication Networks  
Although OpenSSL could provide a freely available implementation of the SSL/TLS protocol, the crypto functions, such as symmetric key ciphers, are extremely compute-intensive operations.  ...  Although there are lots of excellent works with the objective of SSL/TLS hardware acceleration, they focus on the dedicated hardware design of accelerators.  ...  Acknowledgments This work is supported by the National Natural Science Foundation of China (61502061), Chongqing Application Foundation and Research in Cutting-Edge Technologies (cstc2015jcyjA40016), and  ... 
doi:10.1155/2018/7631342 fatcat:vjxul2nl5jfbfek6snwz7em2g4
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