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VLSI Implementation of Neural Classifiers

Arun Rao, Mark R. Walker, Lawrence T. Clark, L. A. Akers, R. O. Grondin
1990 Neural Computation  
Classifier algorithms employing a finite number of clusters of fixed radius will be subopti- mal for non-Gaussian sample classes.  ...  Communicated by Joshua Alspector and Gail Carpenter VLSI Implementation of Neural Classifiers Arun Rao Mark R. Walker Lawrence T. Clark L. A. Akers R. O.  ... 
doi:10.1162/neco.1990.2.1.35 fatcat:cib7fia6gzcp7elcqnxnk4adx4

Gram-Schmidt-based QR decomposition for MIMO detection: VLSI implementation and comparison

P. Luethi, C. Studer, S. Duetsch, E. Zgraggen, H. Kaeslin, N. Felber, W. Fichtner
2008 APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems  
This paper presents an optimized fixed-point VLSI implementation of the modified Gram-Schmidt (MGS) QRD algorithm that incorporates regularization and additional sorting of the MIMO channel matrix.  ...  The comparison of the implementation results clearly showed superiority of the GR-based VLSI solution in terms of area, processing cycles, and throughput.  ...  architecture non-critical.  ... 
doi:10.1109/apccas.2008.4746151 dblp:conf/apccas/LuethiSDZKFF08 fatcat:jmyxujs46ndyzow7t4h347xqia

Binary partition algorithms and VLSI architectures for median and rank order filtering

C.L. Lee, C.-W. Jen
1993 IEEE Transactions on Signal Processing  
They can be implemented by simple and regular modules in VLSI.  ...  A class of selection algorithms by binary partition is very efficient for median and rank order filtering. A unified discussion of . IEEE Log Number 9210117 these algorithms is presented.  ...  Logic gates and Counting Logic gates and Mask +set Logic gates "1" counter O(Nn) "0" counter O(Nn) "0" & "1" counter O(Nn) O W ) Subtracter 0 (Nn) Subtracter O W ) Subiadd  ... 
doi:10.1109/78.236516 fatcat:ecsymobh2bactec6iqjituxopq

A taxonomy of parallel sorting

Dina Bitton, David J. DeWitt, David K. Hsaio, Jaishankar Menon
1984 ACM Computing Surveys  
We propose a taxonomy of parallel sorting that encompasses a broad range of array-and file-sorting algorithms.  ...  We analyze how research on parallel sorting has evolved, from the earliest sorting networks to shared memory algorithms and VLSI sorters.  ...  Parallel Disk Sorting The notion of a sorted file stored on a magnetic disk requires that physical order be defined since disks are not sequential storage media.  ... 
doi:10.1145/2514.2516 fatcat:dc2bhjocynep5mfp3ntak3cfrq

Fast algorithms for linear prediction and system identification filters with linear phase

S. Marple
1982 IEEE Transactions on Acoustics Speech and Signal Processing  
They can be implemented by simple and regular modules in VLSI.  ...  A class of selection algorithms by binary partition is very efficient for median and rank order filtering. A unified discussion of . IEEE Log Number 9210117 these algorithms is presented.  ...  Logic gates and Counting Logic gates and Mask +set Logic gates "1" counter O(Nn) "0" counter O(Nn) "0" & "1" counter O(Nn) O W ) Subtracter 0 (Nn) Subtracter O W ) Subiadd  ... 
doi:10.1109/tassp.1982.1163987 fatcat:amvihsxvi5bxnf7x6rs2fi4uxe

Sorting binary numbers in hardware - A novel algorithm and its implementation

Srikanth Alaparthi, Kanupriya Gulati, Sunil P. Khatri
2009 2009 IEEE International Symposium on Circuits and Systems  
A rank matrix of size n × n is used to store ranks. Each row of the rank matrix corresponds to one of the n numbers, and it stores a single non-zero entry.  ...  This paper describes a novel algorithm for sorting binary numbers in hardware, along with a custom VLSI hardware design for the same.  ...  The position of this non-zero value corresponds to the rank of the i th number.  ... 
doi:10.1109/iscas.2009.5118240 dblp:conf/iscas/AlaparthiGK09 fatcat:6f4mbj2y2jbxzeqybiwstug3ra

VLSI architecture of leading eigenvector generation for on-chip principal component analysis spike sorting system

Tung-Chien Chen, Wentai Liu, Liang-Gee Chen
2008 2008 30th Annual International Conference of the IEEE Engineering in Medicine and Biology Society  
Based on the iterative eigenvector distilling algorithm, the proposed flipped structure enables the low cost and low power implementation by discarding the division and square root hardware units.  ...  On-chip spike detection and principal component analysis (PCA) sorting hardware in an integrated multi-channel neural recording system is highly desired to ease the bandwidth bottleneck from high-density  ...  This approach achieves more than 100fold data reduction while preserving the neuron signature for discrimination and classification of individual neuron signal sources.  ... 
doi:10.1109/iembs.2008.4649882 pmid:19163385 fatcat:lo2if3eiqzhgflbfinq2v5a6ri

High-speed median filter designs using shiftable content-addressable memory

Chen-Yi Lee, Po-Wen Hsieh, Jer-Min Tsai
1994 IEEE transactions on circuits and systems for video technology (Print)  
To reach the goal of high-speed data sorting, an optimized delete-and-insert algorithm is derived and then mapped onto shiftable content-addressable memory architecture.  ...  The median is obtained by first sorting input sequences and then selecting identified order according to the number of inputs.  ...  Also the MPC support from Chip Implementation Center (CIC) of NSC is acknowledged.  ... 
doi:10.1109/76.340196 fatcat:4flca4z4ang5xpcr75isr6rpyq

Algorithm and implementation of the K-best sphere decoding for MIMO detection

Zhan Guo, P. Nilsson
2006 IEEE Journal on Selected Areas in Communications  
As a low complexity MIMO decoding algorithm, the KSE is shown to be suitable for very large scale integration (VLSI) implementations and be capable of supporting soft outputs.  ...  The implementation results show that it is feasible to achieve near-ML performance and high detection throughput for a 4 4 16-QAM MIMO system using the proposed algorithms and the VLSI architecture with  ...  Burg (ETH, Zurich) for the helpful discussions on the depth-first and breadth-first algorithms. They would also like to thank the anonymous reviewers for their careful review and precious comments.  ... 
doi:10.1109/jsac.2005.862402 fatcat:effuoan7irbvppsm6k5xxplbg4

Design and FPGA-Implementation of Minimum PED Based K-Best Algorithm in MIMO Detector

Poornima Ramasamy, Mahabub Basha Ahmedkhan, Mounika Rangasamy
2016 Circuits and Systems  
The pipelined VLSI architecture is the best suited for implementation because the expansion and sorting cores are data driven.  ...  The proposed algorithm is independent of the number of transmitting/receiving antennas and constellation size.  ...  Assuming that initial parent node is non-numerical value.  ... 
doi:10.4236/cs.2016.76052 fatcat:ofdefcsbxzf3xfni65fooyx5wu

VLSI Implementation of Contour Extraction from Real Time Image Sequences [chapter]

Elmar Melcher, Lírida Naviner, João Marques Carvalho, Jean François Naviner, Ricardo A. S. Moreira, Yuri Mello Villar, Marcos Morais
1997 VLSI: Integrated Systems on Silicon  
In this work a parallel architecture is proposed for VLSI implementation of a dataflow algorithm for 20 boundary (or contour) detection.  ...  The algorithm works on the gradient image and uses a set of primitive paths to generate all possible contour paths on a neighborhood defined by a 5x5 window.  ...  A compromise solution to the above problem may be a hybrid architecture, where vertex detection would be followed by a non data-flow procedure in charge of assigning detected vertex to objects.  ... 
doi:10.1007/978-0-387-35311-1_3 fatcat:voq35ct55jcjxorygmpmzjes3a

Tight bounds on the complexity of parallel sorting

Tom Leighton
1984 Proceedings of the sixteenth annual ACM symposium on Theory of computing - STOC '84  
of algorithms, and logics and semantics of programs .  ...  AJTAI, M .; KOMLOS, J . ; AND SZEMEREDI, E . Sorting in c log n parallel steps.  ...  Bose and Nelson [1] produced a sorting network of size O(n bog23 ), and Floyd and Knuth produced one of size 0(n 1 + c/log05n) [2] .  ... 
doi:10.1145/800057.808667 dblp:conf/stoc/Leighton84 fatcat:hcgpsyo5qfb2fhnycpx6b6yblu

Tight Bounds on the Complexity of Parallel Sorting

Tom Leighton
1985 IEEE transactions on computers  
of algorithms, and logics and semantics of programs .  ...  AJTAI, M .; KOMLOS, J . ; AND SZEMEREDI, E . Sorting in c log n parallel steps.  ...  Bose and Nelson [1] produced a sorting network of size O(n bog23 ), and Floyd and Knuth produced one of size 0(n 1 + c/log05n) [2] .  ... 
doi:10.1109/tc.1985.5009385 fatcat:wqnphxx3yjbkvddsk2fxgg7kne

A bit-level pipelined VLSI architecture for the running order algorithm

Chun-Te Chen, Liang-Gee Chen, Jue-Hsuan Hsiao
1997 IEEE Transactions on Signal Processing  
The pipelined cycle of the proposed architecture is merely equivalent to the delay time of a pair of 1-bit comparisons that is independent on the window size and the signal resolution.  ...  In this correspondence, a bit-level pipelined VLSI architecture for the running order algorithm is presented.  ...  The authors are with the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C.Publisher Item Identifier S 1053-587X(97)05801-7.  ... 
doi:10.1109/78.611236 fatcat:ayqtnxapubab5esrb6de2mlzo4

Beamspace Channel Estimation for Massive MIMO mmWave Systems: Algorithm and VLSI Design [article]

Seyed Hadi Mirfarshbafan, Alexandra Gallyas-Sanhueza, Ramina Ghods, Christoph Studer
2020 arXiv   pre-print
Simulation results for line-of-sight (LoS) and non-LoS mmWave channels reveal that BEACHES performs on par with state-of-the-art channel estimation methods while requiring orders-of-magnitude lower complexity  ...  To demonstrate the effectiveness of BEACHES in practice, we develop a very large-scale integration (VLSI) architecture and provide field-programmable gate array (FPGA) implementation results.  ...  Nevertheless, the channel vector remains to be sparse in the non-LoS case. C.  ... 
arXiv:1910.00756v2 fatcat:se3yuy2xmbdntbz6bwwl5l6efm
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