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DYPP---A VLSI supercomputer architecture supporting two-level fault tolerance, program graph injection and data levitation concepts

Marius V. A. Hăncu, Kenneth C. Smith
1986 Proceedings of the 1986 ACM fourteenth annual conference on Computer science - CSC '86  
In this ease, the program graph is continuously injected in • flow fashion to interact with the flow of data which is said to become levitating.  ...  It is generally accepted that in the environment of a VLSI array of processors the interconnections are much more reliable than the processing elements (PEs) themselves.  ...  , as well as providing the input data flow and accepting the results data flow.  ... 
doi:10.1145/324634.325215 dblp:conf/acm/HancuS86 fatcat:kivbphgtv5ayvdx4jnc4rqylmq

Design of fast motion estimation algorithm based on hardware consideration

Zhongli He, M.L. Liou
1997 IEEE transactions on circuits and systems for video technology (Print)  
In this paper, we introduce a fast BMME algorithm based on the consideration of hardware implementation. We use a one-dimensional (1-D) systolic array as the basic computing engine.  ...  We propose a checking-vector-based search strategy and show that it can achieve a better algorithmic performance and can be very cost-effective in terms of hardware implementation for low bit-rate video  ...  That means the CV4SS algorithm is more robust than NTSS. IV. THE PROPOSED VLSI ARCHITECTURE Fig. 2(a) shows the proposed architecture.  ... 
doi:10.1109/76.633505 fatcat:dhqiyew32be2zjhfqopdsgqqa4

Teaching processor architecture with a VLSI perspective

Mircea R. Stan, Kevin Skadron
2002 Proceedings of the 2002 workshop on Computer architecture education Held in conjunction with the 29th International Symposium on Computer Architecture - WCAE '02  
This paper proposes a new approach to teaching computer architecture by placing an explicit emphasis on circuit and VLSI aspects.  ...  This approach has the potential to enhance the teaching of both architecture and VLSI classes, to improve collaboration between CS and ECE departments and to lead to a better understanding of the current  ...  Yet the circuit-design exigencies that profoundly impact the implementation of architecture-level concepts often receive little consideration.  ... 
doi:10.1145/1275462.1275467 dblp:conf/wcae/StanS02 fatcat:qbcgyhnow5hhhlar5zl2tyvjx4

On the design of algorithms for VLSI systolic arrays

D.I. Moldovan
1983 Proceedings of the IEEE  
The mapping procedure is based on the mathematkal tran8fonnati011~ of m d a sets and data d e pendencevectors. Neasgymdsuff&ntconditionsfortheexistenQ dependences.  ...  decomposition of amatrixwhiChledstocon8tmtdrtadependenQW~dsecondly is the dynamic pqnmmiug which leads to dependences which are ~~o n t t t e i a d e x s e t P a d u e m o r e~t t o b e m . p p e d m t o VLSI  ...  Since we consider here only the global model, it will be sufficient to show that the data flow through the VLSI network is correct.  ... 
doi:10.1109/proc.1983.12532 fatcat:dcb7bzdhibaulh5y6vmesduvym

DVPP: a VLSI dynamic-graph ensemble machine

Hancu, K. C. Smith
1988 Proceedings of the 2nd international conference on Supercomputing - ICS '88  
In this case. the program graph is continuously injected (embedded) in a flow fashion to interact with the flow of data and intermediate results, which flow is said to become levitating.  ...  A new VLSI supercomputer architecture, DYPP (DYnamically Programmable multi-Processor), was introduced, with the unique property of being able lo embed, and execute directly. program graphs both statically  ...  As a matter of fact, considerable current research in VLSI algorithms is directed toward creating algorithms matching the VLSI constraints c291, c37l. [451.  ... 
doi:10.1145/55364.55373 dblp:conf/ics/HancuS88 fatcat:m3erwiz2nngr7cto45vn73w6x4

FPGA Design Framework Combined with Commercial VLSI CAD

Qian ZHAO, Kazuki INOUE, Motoki AMAGASAKI, Masahiro IIDA, Morihiro KUGA, Toshinori SUEYOSHI
2013 IEICE transactions on information and systems  
First, VPR cannot directly support most newly developed FPGA architectures, and modifying the C-coded VPR so that it can be used to evaluate a number of new architectures is time consuming.  ...  With these files, the FPGA IP can be evaluated with commercial VLSI CAD systems with high accuracy and reliability.  ...  Acknowledgments This work was supported by the VLSI Design and Education Center (VDEC) of the University of Tokyo in collaboration with Synopsys, Inc., Cadence Design System, Inc., and Mentor Graphics,  ... 
doi:10.1587/transinf.e96.d.1602 fatcat:quem56ufirhpxma7ts23owiz7y

Cost-effective VLSI architectures and buffer size optimization for full-search block matching algorithms

Yuan-Hau Yeh, Chen-Yi Lee
1999 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Starting from an overlapped data flow of search area, both systolic-and semisystolicarray architectural solutions are derived.  ...  This paper presents two efficient very large scale integration (VLSI) architectures and buffer size optimization for full-search block matching algorithms.  ...  SA VLSI Architecture From the derived overlapped data flow, it can be found that search data from two different rows (or columns) are needed as a boundary candidate is detected.  ... 
doi:10.1109/92.784096 fatcat:ozzsnkn5enfsxcsanauthuvrdi

Algorithm and VLSI Architecture Design for MPEG-Like High Definition Video Coding‐AVS Video Coding from Standard Specification to VLSI Implementation [chapter]

Haibing Yin
2013 Advanced Video Coding for Next-Generation Multimedia Services  
The Architecture of Mode Decision with IP Data Dependency Removal in VLSI Architecture An important problem in mode decision VLSI architecture design is the block level data dependency due to intra prediction  ...  The hardware oriented algorithm is customized under the hardware architecture constraint, with data organization and data flow considered.  ... 
doi:10.5772/52965 fatcat:zawp3ga67ngwvc7qapjdafvlwi

On the design of large receiver and transmitter arrays for OE-VLSI applications

M.B. Venditti, D.V. Plant
2003 Journal of Lightwave Technology  
(OE-VLSI) applications is described, and the use of optically and electrically differential architectures is advocated.  ...  We show that the operational yield of large receiver arrays is maximized through the use of an optically and electrically differential architecture.  ...  The digital circuitry is an integral part of an OE-VLSI chip and strongly influences the design environment and the design flow of the optical receivers and transmitters.  ... 
doi:10.1109/jlt.2003.822234 fatcat:sxyslgmglzhazk2s3mpylstxya

Memristor MOS Content Addressable Memory (MCAM) Design Using 22nm VLSI Technology
IJARCCE - Computer and Communication Engineering

KomalJ. Anasane, Dr.UjwalaA. Kshirsagar
2015 IJARCCE  
This applicability influences the architecture of CAM systems, there is no loss of stored data even if the power supply of CAM blocks are disabled.Sake, memristorbased CAM cells have the potential for  ...  This mix provides a newheadway predisposition for the stumbling-block and modeling of memristor based CAM (MCAM) using a combination of MOS devices to form a core of a memory or logic cell that forms the  ...  This behavior influences the architecture of CAM systems, where the power source of CAM blocks can be deactivated without damage of stored data.  ... 
doi:10.17148/ijarcce.2015.4346 fatcat:ts7kbsrx65gedbqsfggbuik4wq

Low power VLSI sequential circuit architecture using critical race control

Menahem Lowy, Neal Butler, Rosanne Tinkler
2003 Proceedings of the 13th ACM Great Lakes Symposium on VLSI - GLSVLSI '03  
This paper describes a new architecture for VLSI sequential circuits and a method to control the critical races that appears subsequently in their feedback loops.  ...  When used with asynchronous circuits this architecture enables the operation of circuits that are unusable using present techniques.  ...  Copyright 2003 ACM 1-58113-677-3/03/0004…$5.00. additional benefits of that architecture were developed. Presently the architecture is implemented in a chip that is part of a larger system.  ... 
doi:10.1145/764808.764827 dblp:conf/glvlsi/LowyBT03 fatcat:jitsjvnftndj3dz2ljkr7u3idm

Low power VLSI sequential circuit architecture using critical race control

Menahem Lowy, Neal Butler, Rosanne Tinkler
2003 Proceedings of the 13th ACM Great Lakes Symposium on VLSI - GLSVLSI '03  
This paper describes a new architecture for VLSI sequential circuits and a method to control the critical races that appears subsequently in their feedback loops.  ...  When used with asynchronous circuits this architecture enables the operation of circuits that are unusable using present techniques.  ...  Copyright 2003 ACM 1-58113-677-3/03/0004…$5.00. additional benefits of that architecture were developed. Presently the architecture is implemented in a chip that is part of a larger system.  ... 
doi:10.1145/764825.764827 fatcat:cl5g2dqssfak7fpzesssvtc6yq

VLSI architecture: past, present, and future

W.J. Dally, S. Lacy
1999 Proceedings 20th Anniversary Conference on Advanced Research in VLSI  
Data similar to those in 4. Many important contributions were made beyond the few that I cite here. 5. They are an example of processors that are not yet to the point of diminishing returns.  ...  This paper examines the impact of VLSI technology on the evolution of computer architecture and projects the future of this evolution.  ...  The work of the many students and staff involved in the MIT J-Machine and M-Machine projects greatly influenced the thoughts presented here.  ... 
doi:10.1109/arvlsi.1999.756051 dblp:conf/arvlsi/DallyL99 fatcat:wcpnutla2ravljkyjz64uang5m

Efficient Hierarchical Motion Estimation Algorithm and Its VLSI Architecture

Bing-Fei Wu, Hsin-Yuan Peng, Tung-Lung Yu
2008 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
HMEA exhibits regular data flow and is suitable for hardware implementation.  ...  An efficient VLSI architecture that includes an averaging filter to downsample the image and two 2-D semisystolic processing element arrays to determine the sum of absolute difference in pipeline is also  ...  GEA has a more regular data flow than SEA.  ... 
doi:10.1109/tvlsi.2008.2000526 fatcat:6sy4sdolzrc5detgzugkog5f7m

Wavelet transform architectures: A system level review [chapter]

M. Ferretti, D. Rizzo
1997 Lecture Notes in Computer Science  
Indeed, common VLSI cost functions (such as AT ~-) are insufficient to evaluate architectures for compression.  ...  Such approaches can be substituted with more standard ones, if data reordering is mandatory to apply a good quantization strategy. An upcoming commercial solution offers a sound comparison paradigm.  ...  The data flow' graph of the low pass and high pass filters have been optimized for that kernel, both for the forward and the backward transform.  ... 
doi:10.1007/3-540-63508-4_108 fatcat:ql2uhz3f2rdyjk2jkxd5jh7sou
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