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An Efficient Motion Adaptive De-interlacing and Its VLSI Architecture Design

Hongbin Sun, Nanning Zheng, Chenyang Ge, Dong Wang, Pengju Ren
2008 2008 IEEE Computer Society Annual Symposium on VLSI  
Based on our method, the high speed VLSI architecture has been designed and implemented.  ...  With a Gaussian filter, the motion detection can eliminate the influence of noise.  ...  The VLSI architecture has been designed to realize real-time interpolation for consumer video applications. The block diagram of this hardware architecture is showed in Figure 7 .  ... 
doi:10.1109/isvlsi.2008.46 dblp:conf/isvlsi/SunZGWR08 fatcat:hp53liw4ofgkfa6nn642hyqmhq

An area-efficient median filtering IC for image/video applications

P.-W. Hsieh, J.-M. Tsai, C.-Y. Lee
1993 IEEE transactions on consumer electronics  
An area-efficient IC for high-throughput median filtering applications is presented in this paper.  ...  A proto-type chip for 64 input samples is implemented and tested. Results show that clock rate up to 50 MHz can be achieved using a 1.2 pm CMOS double metal technology.  ...  Acknowledgement: The authors would like to thank their colleagues within the VLSI/CAD group for many fruitful discussions. Also the MPC services from Chip Implementation Center is acknowledged.  ... 
doi:10.1109/30.234627 fatcat:j5wc2uhsdrfqnfdh4cuonau6ou

High-speed median filter designs using shiftable content-addressable memory

Chen-Yi Lee, Po-Wen Hsieh, Jer-Min Tsai
1994 IEEE transactions on circuits and systems for video technology (Print)  
This paper presents a very efficient VLSI architecture for real-time median filtering as requested in many imagefvideo applications.  ...  A proto-type chip for 64 samples based on this architecture has been implemented and tested. Results show that a clock rate up to 50 MHz can be achieved using a 1.2 p m CMOS double metal technology.  ...  Also the MPC support from Chip Implementation Center (CIC) of NSC is acknowledged.  ... 
doi:10.1109/76.340196 fatcat:4flca4z4ang5xpcr75isr6rpyq

Real time hardware co-simulation of Edge Detection for video processing system

Yahia Said, Taoufik Saidani, Fethi Smach, Mohamed Atri
2012 2012 16th IEEE Mediterranean Electrotechnical Conference  
on motion which is useful for improving the speed and precision of the recognition.  ...  Therefore, the proposed system presents that the VLSI is capable for extracting motion features from moving images.  ...  The median filter is known as a very powerful rank-order filter but is computationally very expensive filter and making threshold determination the bottleneck of this system.  ... 
doi:10.1109/melcon.2012.6196563 fatcat:kjeyjd4yyjaglitoh7ylox26h4

Table of contents

2004 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat No 04CH37512) ISCAS-04  
Willingham, Izzet Kale, University of Westminster, United Kingdom VLSI-L2: VIDEO VLSI-L2.1: A DISTRIBUTED TS-MUX ARCHITECTURE FOR MULTI-CHIP EXTENSION ................................II -261 BEYOND THE  ...  , Australia VLSI-L6.3: A REAL-TIME VLSI MEDIAN FILTER EMPLOYING TWO-DIMENSIONAL ....................................II -349 BIT-PROPAGATING ARCHITECTURE Hideo Yamasaki, Tadashi Shibata, University of Tokyo  ... 
doi:10.1109/iscas.2004.1328114 fatcat:xmvsmkhxgbb55ftuygqomthikm

Tera-Scale Performance Machine Learning SoC (MLSoC) With Dual Stream Processor Architecture for Multimedia Content Analysis

Tse-Wei Chen, Chi-Sun Tang, Sung-Fang Tsai, Chen-Han Tsai, Shao-Yi Chien, Liang-Gee Chen
2010 IEEE Journal of Solid-State Circuits  
Different from traditional VLSI architectures, it focuses on the coacceleration of computer vision and machine learning algorithms, and two stream processors with massively parallel processing elements  ...  A new machine learning SoC (MLSoC) for multimedia content analysis is implemented with 16-mm 2 area in 90-nm CMOS technology.  ...  Hsieh for process support and the National Chip Implementation Center (CIC) for EDA tool support.  ... 
doi:10.1109/jssc.2010.2067910 fatcat:i2wxnxmfizg2zfqjejnukfdf5y

A High-Performance Architecture of Motion Adaptive De-interlacing with Reliable Interfield Information

C.-c. LIN, M.-h. SHEU, H.-k. CHIANG, C.-J. WEI, C. LIAW
2007 IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences  
The proposed architecture has been implemented as a VLSI chip based on UMC 0.18-µm CMOS technology process. The total gate count is 30114 and its layout area is about 710 × 710-µm.  ...  The third component, spatial-temporal edge-based median filter, is used to deal with the interpolation for those motion pixels.  ...  Finally the architecture was implemented as a VLSI chip. y), and m 1 1 = |a − f |, m 2 = |b − e|, m 3 = |c − d|, m 4 = |p − u|, m 5 = |q − t|, and m 6 = |r − s|.  ... 
doi:10.1093/ietfec/e90-a.11.2575 fatcat:skyzpdtih5dadbiukjlmeug5je

FPGA IMPLEMENTATION AND ANALYSIS OF IMPULSE NOISE REDUCTION IN IMAGES

Thirumurugan
2014 American Journal of Applied Sciences  
The hardware architecture for this design is proposed and its performance is analyzed with different FPGA Processors in terms of slices, LUTs and power consumption.  ...  The proposed hardware architecture consumes 1728 gates and power consumption of 159.95 mW.  ...  Figure 3 shows the block diagram of VLSI architecture for optimal detection algorithm.  ... 
doi:10.3844/ajassp.2014.1041.1048 fatcat:7bizwjn6i5gl7fjn3uesuwvxya

Partial-result-reuse architecture and its design technique for morphological operations with flat structuring elements

Shao-Yi Chien, Shyh-Yih Ma, Liang-Gee Chen
2005 IEEE transactions on circuits and systems for video technology (Print)  
The maximum frequency of the chip is 200 MHz in simulation, while processing speed of 550 morphological operations/s on a 720 480 frame can be achieved.  ...  This paper proposes a new architecture named Partial-Result-Reuse (PRR) architecture for mathematical morphological operations with flat structuring elements.  ...  Therefore, a pseudomedian filter, whose properties are similar to those of median filter, has been proposed [26] .  ... 
doi:10.1109/tcsvt.2005.852622 fatcat:mu6rqqbiqza2rppg5ntytvnfxq

Efficiency Analysis for a Mixed-Signal Focal Plane Processing Architecture

William H. Robinson, D. Scott Wills
2005 Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology  
Implementations of the focal plane architecture achieve up to 81x higher area efficiency and up to 11x higher energy efficiency when compared to traditional TI DSP chips.  ...  This paper analyzes the area-time efficiency, the area efficiency, and the energy efficiency of a mixed-signal, SIMD focal plane processing architecture that executes front-end image applications with  ...  Acknowledgment The first author would like to acknowledge the generous support of this research from the Ford Foundation Dissertation Fellowship for Minorities and the Facilitating Academic Careers in  ... 
doi:10.1007/s11265-005-6251-5 fatcat:5wivm5qpzvbhjeldmiy5unixmy

Algorithm and VLSI Architecture Design for MPEG-Like High Definition Video Coding‐AVS Video Coding from Standard Specification to VLSI Implementation [chapter]

Haibing Yin
2013 Advanced Video Coding for Next-Generation Multimedia Services  
On-chip SRAM consumption for the reference pixels in HD video encoder is dramatically high.  ...  There are huge data exchanges between external memory and on-chip SRAM buffer for real-time video coding.  ... 
doi:10.5772/52965 fatcat:zawp3ga67ngwvc7qapjdafvlwi

An Adaptive Pipeline Processor For Real-Time Image Processing

Neil Storey, Richard C. Staunton, Michael J. W. Chen
1990 Automated Inspection and High-Speed Vision Architectures III  
The processor concerned accepts digitised video information from any standard video source and performs real-time processing on it.  ...  Since each PE will be implemented as a single, identical, VLSI circuit, the arrangement is potentially very cost effective.  ...  VLSI chip.  ... 
doi:10.1117/12.969953 fatcat:npmd3wnndned7bujptjrifm2rq

VLSI Implementation of a Cost-Efficient Near-Lossless CFA Image Compressor for Wireless Capsule Endoscopy

Shih-Lun Chen, Tse-Yen Liu, Chia-Wei Shen, Min-Chun Tuan
2016 IEEE Access  
In this paper, a novel near-lossless color filter array (CFA) image compression algorithm based on JPEG-LS is proposed for VLSI implementation.  ...  The VLSI architecture of the proposed image compressor consists of a register bank, a pixel restoration module, a predictor, a run mode module, and an entropy encoder.  ...  VLSI ARCHITECTURE Based on the algorithm mentioned above, the architecture of the proposed near-lossless image encoder design is shown in Fig. 6 .  ... 
doi:10.1109/access.2016.2638475 fatcat:x2fcazeytjdllpgbfifemqdppi

TAGIPS, An Adaptable Parallel Processor For Imaging Applications

Pekka Hanninen, Jouko Viitanen, Juha Salo, Jarmo Takala, Michael J. W. Chen
1989 Automated Inspection and High-Speed Vision Architectures II  
The new generation 32 bit signal processing chips have architectural features that make them suitable for image processing purposes.  ...  In this paper we present a fast parallel processor for a PC bus.  ...  Our example is the calculation of a hybrid FIR-median filter. CALCULATION OF A FIVE POINT MEDIAN WITH RRLCA Median based hybrid filters are good in filtering noisy images.  ... 
doi:10.1117/12.949007 fatcat:kbhmonb355edbl26f6n4txix3u

Motion Segmentation and Tracking with Edge Relaxation and Optimization using Fully Parallel Methods in the Cellular Nonlinear Network Architecture

László Czúni, Tamás Szirányi
2001 Real-time imaging  
The proposed system is ready to be implemented in a Cellular Nonlinear Network chip-set architecture.  ...  I n this paper we outline a fully parallel and locally connected computation model for the segmentation of motion events in video sequences based on spatial and motion information.  ...  Since other non-linear filters, such as rank order filters, can also be implemented in our parallel framework [17] , we will use them (e.g., median filter) for oversegmentation purposes.  ... 
doi:10.1006/rtim.2000.0222 fatcat:tqgv3jnltjcazctycbgxkca4rq
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