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Verification of Abstracted Instruction Cache of TITAC2: A Case Study [chapter]

Tomohiro Yoneda
2000 IFIP Advances in Information and Communication Technology  
In this paper, we demonstrate the formal verification of a practical timed asynchronous circuit.  ...  The target circuit is obtained by abstracting the instruction cache subsystem of areal asynchronous processor, TITAC 2. We also show several techniques to improve our verification method.  ...  Masashi Kuwako, Rafael Morizawa, and Hiroshi Ryu for valuable discussions. 6.  ... 
doi:10.1007/978-0-387-35498-9_33 fatcat:xa5orgjdp5gsviwdn2u7q7g4k4

Automatic Derivation of Timing Constraints by Failure Analysis [chapter]

Tomohiro Yoneda, Tomoya Kitai, Chris Myers
2002 Lecture Notes in Computer Science  
This work proposes a technique to automatically obtain timing constraints for a given timed circuit to operate correctly.  ...  A designated set of delay parameters of a circuit are first set to sufficiently large bounds, and verification runs followed by failure analysis are repeated.  ...  for helpful comments to model GasP circuits.  ... 
doi:10.1007/3-540-45657-0_15 fatcat:vedfsd3hbzapbjan3ij6ejcunm

Modular verification of timed circuits using automatic abstraction

Hao Zheng, E. Mercer, C. Myers
2003 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
This paper presents a new approach for verification of timed circuits using automatic abstraction. This approach partitions the design into modules, each with constrained complexity.  ...  This approach converts a verification problem with big exponential complexity to a set of sub-problems, each with small exponential complexity.  ...  ACKNOWLEDGMENTS We would like to thank Wendy Belluomini of IBM and Tomohiro Yoneda of the Tokyo Institute of Technology for their helpful comments.  ... 
doi:10.1109/tcad.2003.816214 fatcat:wckiciqqjzew5khdxlixd47haa

Algorithms for automatic generation of relative timing constraints

Yang Xu
2012
A relative timing (RT) based asynchronous circuit design flow using traditional synchronous commercial CAD tools was recently proposed.  ...  This dissertation presents an algorithm that automatically generates a set of relative timing constraints to guarantee the correctness of a circuit with the aid of a formal verification engine -Analyze  ...  Relative timing is the key hub of all the other research in his group.  ... 
doi:10.26053/0h-02kc-kh00 fatcat:o4gdfnhi3fg2tpkhxvzq35nfaa