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Systematic HDL Design of a S-? Fractional-N Phase-Locked Loop for Wireless Applications

Ahmed El Oualkadi, Denis Flandre
<span title="">2008</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/k4pq3zhykrd3hdhey2qhybwinu" style="color: black;">2008 IEEE Computer Society Annual Symposium on VLSI</a> </i> &nbsp;
The HDL models of critical PLL blocks have been described in VHDL-AMS to predict the different specifications of the PLL.  ...  This paper discusses a systematic design of afractional-N Phase-Locked Loop based on HDL behavioral modeling.  ...  By using VHDL-AMS, the architecture of each block has been defined and simulated. Fig. 6 shows the modeling approach used. The CP and PFD are modeled in VHDL-AMS.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/isvlsi.2008.40">doi:10.1109/isvlsi.2008.40</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/isvlsi/OualkadiF08.html">dblp:conf/isvlsi/OualkadiF08</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/nfbgugw7szhsnpeg64zjdmakgm">fatcat:nfbgugw7szhsnpeg64zjdmakgm</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20200318174915/https://hal.inria.fr/hal-00947400/document" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/19/8e/198e17278d9c969ef4b52302b3790e1823c06ac7.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/isvlsi.2008.40"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Hardware Description Language Design Of Σ-Δ Fractional-N Phase-Locked Loop For Wireless Applications

Ahmed El Oualkadi, Abdellah Ait Ouahman
<span title="2009-04-26">2009</span> <i title="Zenodo"> Zenodo </i> &nbsp;
The HDL models of critical PLL blocks have been described in VHDL-AMS to predict the different specifications of the PLL.  ...  This paper discusses a systematic design of a Σ-Δ fractional-N Phase-Locked Loop based on HDL behavioral modeling.  ...  By using VHDL-AMS, the architecture of each block has been defined and simulated. Fig. 6 shows the modeling approach used. The CP and PFD are modeled in VHDL-AMS.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.5281/zenodo.1080399">doi:10.5281/zenodo.1080399</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/dqyvgow74vgc3pivd5kjhto2eu">fatcat:dqyvgow74vgc3pivd5kjhto2eu</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20201223010342/https://zenodo.org/record/1080400/files/13048.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/ae/41/ae416da388dbb04b613840b9319ab2057a3b1260.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.5281/zenodo.1080399"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> zenodo.org </button> </a>

Analysis of a Third-Order Charge-Pump Phase-Locked Loops used for Wireless Sensor Transceiver

Intissar Toihria, Rim Ayadi, Mohamed Masmoudi
<span title="2013-09-18">2013</span> <i title="Foundation of Computer Science"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/b637noqf3vhmhjevdfk3h5pdsu" style="color: black;">International Journal of Computer Applications</a> </i> &nbsp;
This paper, present an exact s-domain model analysis of a Third-Order Charge-Pump Phase-Locked Loops (CP-PLLs) used for wireless sensor transceiver using state equations of Phase Frequency Detector.  ...  The analysis is verified using behavioral simulations with VHDL-AMS in Simplorer.  ...  ACKNOWLEDGMENTS This work was supported by Laboratory of Electronic and Micro-technology Communication (EMC), National School of Engineering Sfax, University of Sfax, Tunisia.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.5120/13394-1036">doi:10.5120/13394-1036</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/yq5mdwf4xfdpblqnsl72axpag4">fatcat:yq5mdwf4xfdpblqnsl72axpag4</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20180604072943/https://research.ijcaonline.org/volume77/number5/pxc3891036.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/03/97/0397b2c0f7487380e653e0c905ea63d47ddb4fb5.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.5120/13394-1036"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

Analogue and mixed-signal extension to SystemC

H. Al-Junaid, T. Kazmierski
<span title="">2005</span> <i title="Institution of Engineering and Technology (IET)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/p4qo74anhjb3bffx42h3l6ve5y" style="color: black;">IEE Proceedings - Circuits Devices and Systems</a> </i> &nbsp;
This paper presents a new methodology that enables extensions of SystemC to the analogue domain and allows modelling of mixed-signal and mixed energy-domain systems at arbitrary levels of abstraction.  ...  Operation of the extended, mixedsignal simulation platform, named SystemC-A, is demonstrated using a suite of numerically difficult AMS examples including a practical, mixed-signal example of a PLL frequency  ...  A number of modelling styles are possible, for example a SPICE-like net-list or VHDL-AMS-like simultaneous equations with a hierarchy of interconnected blocks as in any HDL.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1049/ip-cds:20045204">doi:10.1049/ip-cds:20045204</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/3jlgqe5th5fc5grjnurb4pg2rm">fatcat:3jlgqe5th5fc5grjnurb4pg2rm</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170830013823/https://eprints.soton.ac.uk/260644/1/IEEJournal.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/93/25/93250d43d8e7d182e00d7ccdf3b1f6f641259df4.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1049/ip-cds:20045204"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> Publisher / doi.org </button> </a>

Detection and Evaluation of Deterministic Jitter Causes in CP-PLL?s Due to Macro Level Faults and Pre-Detection Using Simple Methods

Martin John Burbidge
<span title="">2005</span> <i title="Springer Nature"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/dt5ooavfurcrfbcz432scm5wcu" style="color: black;">Journal of electronic testing</a> </i> &nbsp;
The evaluation platform consists of a macro level mixed signal based PLL-Model.  ...  Charge-Pump Phase-locked loops are currently used in a variety of signal generation applications.  ...  Thanks also Agilent for a trial version of the ADVANCED DESIGN SYSTEM 2003A simulation and design package and to Dolphin Integration, Grenoble, Fr, for access to simulation software.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/s10836-005-6356-6">doi:10.1007/s10836-005-6356-6</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/uy7lhxnljvhixitediqmvajyae">fatcat:uy7lhxnljvhixitediqmvajyae</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170808080148/http://www.mjb-rfelectronics-synthesis.com/WebFiles/IMS_JETTA05_MJB.pdf?origin=publication_detail" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/20/f5/20f5f0cf680df15b783130194ee3bca3bb7abd0f.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1007/s10836-005-6356-6"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> springer.com </button> </a>

On behavioral model equivalence checking for large analog/mixed signal systems

Amandeep Singh, Peng Li
<span title="">2010</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/ffbycmiwjfgqbewnyare6s37ru" style="color: black;">2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)</a> </i> &nbsp;
The proposed methodology is then applied for equivalence checking of a PLL as a test case and results are shown which prove the correctness of the proposed methodology. iv DEDICATION to my friends and  ...  This thesis proposes a systematic, hierarchical, optimization based semi-formal equivalence checking methodology for large analog/mixed signal systems such as phase locked loops (PLL), analog to digital  ...  Hardware descriptive languages such as VHDL-AMS [1] and Verilog-AMS [2] have been developed to describe the behavior of analog/mixed signal circuits.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/iccad.2010.5651402">doi:10.1109/iccad.2010.5651402</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/iccad/SinghL10.html">dblp:conf/iccad/SinghL10</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/4wsifmmh7zdale7d5a53lqovfm">fatcat:4wsifmmh7zdale7d5a53lqovfm</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20180719112106/http://oaktrust.library.tamu.edu/bitstream/handle/1969.1/ETD-TAMU-2011-05-9379/SINGH-THESIS.pdf;jsessionid=E5039DF4760E18DCF9DA133A63C35FEF?sequence=2" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/79/49/79490bacd60aeef508abedd7f03d7f53b0204cc7.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/iccad.2010.5651402"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Immunity of modulation schemes in automotive low bitrate power line communication systems

Alexnder Zeichner, Seyyed Ali Hassanpour Razavi, Stephan Frei
<span title="">2015</span> <i title="IEEE"> 2015 IEEE International Symposium on Electromagnetic Compatibility (EMC) </i> &nbsp;
Virtual automotive EMC tests, including Direct Power Injection (DPI), Bulk Current Injection (BCI) and plane wave field coupling (ALSE) were performed to investigate the immunity of the modulation schemes  ...  Transmitter and receiver models for Amplitude Shift Keying (ASK), Frequency Shift Keying (FSK) and Binary Phase Shift Keying (BPSK) are implemented.  ...  by simulation of different digital modulation in VHDL-AMS Fig. 11.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/isemc.2015.7256256">doi:10.1109/isemc.2015.7256256</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/j3gqgh67cjffxokcyip2ztxmeu">fatcat:j3gqgh67cjffxokcyip2ztxmeu</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170810112008/http://www.bordsysteme.tu-dortmund.de/publications/2015_EMC_Europe_Immunity_of_Modulation_Schemes_in_Automotive_Low_Bitrate_Power_Line_Communication_Systems.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/7a/17/7a178141b0f81930992c5c9335200a365f9ad3fa.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/isemc.2015.7256256"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Design tool solutions for mixed-signal/RF circuit design in CMOS nanometer technologies

Georges G.E. Gielen
<span title="">2007</span> <i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/fkjmyf3l45eo5ovjdnpeqpdjd4" style="color: black;">2007 Asia and South Pacific Design Automation Conference</a> </i> &nbsp;
This invited paper describes progress in modeling techniques for design and verification of complex integrated systems, in circuit and yield optimization tools for analog/RF circuits, as well as in signal  ...  The scaling of CMOS technology into the nanometer era enables the fabrication of highly integrated systems, which increasingly contain analog and/or RF parts.  ...  analog higher-level modeling is today enabled by the availability of standardized mixedsignal hardware description languages such as VHDL-AMS and Verilog-AMS, both of which are extensions of the corresponding  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/aspdac.2007.358024">doi:10.1109/aspdac.2007.358024</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/aspdac/Gielen07.html">dblp:conf/aspdac/Gielen07</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/nmg3jf2h7zbyxe5joafirfz724">fatcat:nmg3jf2h7zbyxe5joafirfz724</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170814154756/http://www.cecs.uci.edu/~papers/aspdac07/pdf/p432_4D-1.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/4a/c7/4ac77a9ea256c5e5f7997ae4e13fdd058f8e7d67.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/aspdac.2007.358024"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Radiation Tolerant Electronics

Paul Leroux
<span title="2019-06-27">2019</span> <i title="MDPI AG"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/ikdpfme5h5egvnwtvvtjrnntyy" style="color: black;">Electronics</a> </i> &nbsp;
Research on radiation tolerant electronics has increased rapidly over the last few years, resulting in many interesting approaches to model radiation effects and design radiation hardened integrated circuits  ...  I am also grateful to all of the reviewers who helped in the evaluation of the manuscripts and made very valuable suggestions to improve the quality of the contributions.  ...  I am also grateful to the Electronics Editorial office staff who worked thoroughly to maintain the rigorous peer-review schedule and timely publication.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.3390/electronics8070730">doi:10.3390/electronics8070730</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/wjo5prr5xjeqtlhxlj4kqz5st4">fatcat:wjo5prr5xjeqtlhxlj4kqz5st4</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20200506055034/https://www.mdpi.com/books/pdfdownload/book/1518" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/96/21/96219839df0e276677743d77c08668d30f6818bc.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.3390/electronics8070730"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> mdpi.com </button> </a>

Early SEU fault injection in digital, analog and mixed signal circuits: a global flow

R. Leveugle, A. Ammari
<i title="IEEE Comput. Soc"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/qjrrvry5ubgdlarkymvlxuip6m" style="color: black;">Proceedings Design, Automation and Test in Europe Conference and Exhibition</a> </i> &nbsp;
In this paper, a global analysis flow is proposed, based on a high-level model of the circuit. The possibility to inject transient faults in the different parts is discussed.  ...  The results obtained on a case study are reported to show the feasibility of the injection in analog blocks.  ...  Some results are illustrated in Figure 6 , with an injection at 0.17 ms, after the VCO is locked. The characteristics of the current pulse were RT=100 ps, FT=300 ps, PW=500 ps, PA=10 mA.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/date.2004.1268909">doi:10.1109/date.2004.1268909</a> <a target="_blank" rel="external noopener" href="https://dblp.org/rec/conf/date/LeveugleA04.html">dblp:conf/date/LeveugleA04</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/6lfsehwc5fdghce545vzm2rbae">fatcat:6lfsehwc5fdghce545vzm2rbae</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20170814110455/https://www.cs.york.ac.uk/rts/docs/SIGDA-Compendium-1994-2004/papers/2004/date04/pdffiles/05c_3.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/e0/c9/e0c90635e0f18a0e8d49b386bae3a5d3efb14f00.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/date.2004.1268909"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

2021 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 40

<span title="">2021</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/rl7xk4fwazdrred2difr6v3lii" style="color: black;">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems</a> </i> &nbsp;
The primary entry includes the coauthors' names, the title of the paper or other item, and its location, specified by the publication abbreviation, year, month, and inclusive pagination.  ...  ., +, TCAD Oct. 2021 2063-2076 CMOS logic circuits A VHDL-Based Modeling Approach for Rapid Functional Simulation and Verification of Adiabatic Circuits.  ...  VCO Architectures.  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tcad.2021.3136047">doi:10.1109/tcad.2021.3136047</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/ppooj4g65nc2zonj7szclerc2y">fatcat:ppooj4g65nc2zonj7szclerc2y</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20211217094609/https://ieeexplore.ieee.org/ielx7/43/9620731/09653739.pdf?tp=&amp;arnumber=9653739&amp;isnumber=9620731&amp;ref=" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/09/3e/093e27bf4ef2fd4a3f6d659ac1801d21166e37f3.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/tcad.2021.3136047"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

A design system for RFIC: challenges and solutions

P. Miliozzi, K. Kundert, K. Lampaert, P. Good, M. Chian
<span title="">2000</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/yfvtieuumfamvmjlc255uckdlm" style="color: black;">Proceedings of the IEEE</a> </i> &nbsp;
A close link between schematic, models, and layout is of paramount importance to ensure the accuracy needed for low-power RF design.  ...  We give an overview of the advanced methods and tools currently available for simulation and noise analysis of RF devices. Finally, we show a design example that obtained first-silicon success.  ...  Behavioral simulation, using the new standard languages Verilog-AMS and VHDL-AMS (respectively extensions to the analog and mixed-signal domain of Verilog and VHDL), provides a way to perform high-level  ... 
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/5.888999">doi:10.1109/5.888999</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/wm65f5h2djhjdmvdlyio7uchmy">fatcat:wm65f5h2djhjdmvdlyio7uchmy</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20050129231505/http://www.utdallas.edu:80/~hxz024000/PhaseNoise/2000J_ADesignSystemForRFIC.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/18/ff/18ff8a1e405fc46e1bdfe261bc1810453e4259b3.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/5.888999"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="external alternate icon"></i> ieee.com </button> </a>

Fully FPGA-Based Sensorless Control for Synchronous AC Drive Using an Extended Kalman Filter

Lahoucine Idkhajine, Eric Monmasson, Amira Maalouf
<span title="">2012</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/bt4kk6c6rfgonj36mkvjl5xvbq" style="color: black;">IEEE transactions on industrial electronics (1982. Print)</a> </i> &nbsp;
An Axcelerator FPGA is based on 150nm process technology and consists of a sea of Logic Modules (LMs) and Antifuse interconnection elements.  ...  Appendix A -Compensation of the VSI non-linearities ................................................ 139 Appendix B -Salient Synchronous Machine -Modeling and parameter identification ......... 145 Appendix  ...  Sensorless methods Model-based Signal injection Observer-based method In this case, the extraction of the rotor position and speed is done with the use of observers.  ... 
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CAD solutions and outstanding challenges for mixed-signal and RF IC design

D. Leenaerts, G. Gielen, R.A. Rutenbar
<i title="IEEE"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/ffbycmiwjfgqbewnyare6s37ru" style="color: black;">IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281)</a> </i> &nbsp;
This tutorial paper addresses the problems and solutions that are posed by the design of mixed-signal integrated systems on chip (SoC).  ...  These include problems in mixed-signal design methodologies and flows, problems in analog design productivity, as well as open problems in analog, mixed-signal and RF design, modeling and verification  ...  Other parts of this research have been supported under several Flemish and European projects.  ... 
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Systematic modeling and analysis of telecom frontends and their building blocks Systematic modeling and analysis of telecom frontends and their building blocks Proefschrift voorgedragen tot het behalen van het doctoraat in de toegepaste wetenschappen door Symbols and Abbreviations Conventions

Piet Vanassche
<span title="">2003</span> <span class="release-stage">unpublished</span>
Examples addressed in this text are: the characterization of signal transfers in mixers, the time-varying stability behavior of phase-locked loops (PLLs), noise folding in PLLs, oscillator injection-locking  ...  behavior, oscillator phase noise behavior, modeling an harmonic oscillator's settling behavior.  ...  More recently, describing mixed-signal systems has brought about languages like VHDL-AMS [VHDL] and VERILOG-AMS [VERI] .  ... 
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<a target="_blank" rel="noopener" href="https://web.archive.org/web/20180425134217/https://www.researchgate.net/profile/Piet_Vanassche/publication/258265493_Systematic_modeling_and_analysis_of_telecom_frontends_and_their_building_blocks/links/00b49527a5e55bc15d000000.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/e3/a9/e3a9e07f0afcf47d3b71a6f9192added4f60819c.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a>
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