Filters








978 Hits in 3.9 sec

VHDL Framework for Modeling Fuzzy Automata

Doru Todinca, Daniel Butoianu
2012 2012 14th International Symposium on Symbolic and Numeric Algorithms for Scientific Computing  
of the next state of a FA.  ...  We developed a VHDL framework that can be used for modeling fuzzy automata and for investigating their performance.  ...  In order to simulate in VHDL a circuit or a system, we describe it in terms of design units. The most important design units are the entity and the architecture.  ... 
doi:10.1109/synasc.2012.42 dblp:conf/synasc/TodincaB12 fatcat:anghsztbt5gjjo4hnkv6zsjgku

CUSTOM GRAPHICAL SIMULATORS FOR VHDL LOGIC DESCRIPTIONS AND THE ALTERA NIOS II PROCESSOR

Naraig Manjikian, Valerie Sugarman
2013 Proceedings of the Canadian Engineering Education Association (CEEA)  
The digital logic simulator models switch/pushbutton inputs and LED outputs, and it allows a custom circuit to be specified rapidly in a subset of the VHDL language using predefined signal names and flip-flop  ...  When students in the two courses were surveyed about the custom simulators, a majority of them indicated a degree of enhancement to their learning.  ...  that supported the contributions of Valerie Sugarman, who was a student in the Department of Electrical and Computer Engineering.  ... 
doi:10.24908/pceea.v0i0.4882 fatcat:676af73djfdcfdkhojtdscux7e

A Compound Information Model for High-Level Synthesis [chapter]

Peter Conradi, Nikil Dutt
1995 Electronic Design Automation Frameworks  
This paper will outline the ingredients of a compact information modelfor high-level synthesis (HLS)from high-level languages such as VHDL.  ...  Hence, a necessary future step in this progress of design automation is the standardization on more abstract levels of design.  ...  Summary Our work is an initial effort towards the representation of a compound, integrated model of high-level design information.  ... 
doi:10.1007/978-0-387-34880-3_19 fatcat:vemmcpcigfcjdkhdlijc2mph4a

Considerations on system-level behavioural and structural modeling extensions to VHDL

P.J. Ashenden, P.A. Wilsey
Proceedings International Verilog HDL Conference and VHDL International Users Forum  
Modeling issues that obtain in a system-level design language are identified, including abstraction of data, concurrency, communication and timing, and design refinement.  ...  Some system-level design languages and notations are surveyed, and previous proposals to extend VHDL for system-level design are reviewed.  ...  The Vista OO-VHDL language described by Swamy et al [37] and the OOVHDL language described by Benzakki and Djafri [8] both extend the notion of a VHDL entity, viewing it as a form of class that can  ... 
doi:10.1109/ivc.1998.660679 fatcat:c3owpiktybbavlpcseguzlfj4q

Analog behavior refinement in system centric modeling

Yaseen Zaidi, Christoph Grimm, Jan Haase
2009 2009 IEEE Behavioral Modeling and Simulation Workshop  
SoC designs consisting of analog, digital, mixed signal, RF and software blocks are commonplace.  ...  SystemC AMS offers the potential for a unified modeling approach for such systems through executable specification.  ...  Therefore system level simulation should be augmented with corner views of design areas that are not always discernible.  ... 
doi:10.1109/bmas.2009.5338893 dblp:conf/bmas/ZaidiGH09 fatcat:e7vx6v2icbg6dko2dmfjftaviq

Introducing New Verification Methods into a Company's Design Flow: An Industrial User's Point of View

Robert Lissel, Joachim Gerlach
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
This paper takes an industrial user's point of view and explores the difficulties introducing new verification methods into a company's "naturally grown" and well established design flow -taking into account  ...  Today the task of design verification has become one of the key bottlenecks in hardware and system design.  ...  Another important requirement from a practical point of view is that existing VHDL-based testbench modules may be used unchanged within the new approach.  ... 
doi:10.1109/date.2007.364675 dblp:conf/date/LisselGG07 fatcat:2gj4opjswnautdk2xjbaopxvz4

A Component-Based Design Environment for ESL Design

P. Schaumont, I. Verbauwhede
2006 IEEE Design & Test of Computers  
Application of different IP block categories: coprocessor (a) and multiprocessor (b) design scenarios.  ...  ESL design has many faces A common definition for ESL design is the collection of design techniques for selecting and refining an architecture. But ESL design has many aspects and forms.  ...  We also thank the many students who have experimented with Gezel and whose designs we've mentioned in this article.  ... 
doi:10.1109/mdt.2006.110 fatcat:c7njlid6rffazarsxcgwkpeudq

FoCs – Automatic Generation of Simulation Checkers from Formal Specifications [chapter]

Yael Abarbanel, Ilan Beer, Leonid Gluhovsky, Sharon Keidar, Yaron Wolfsthal
2000 Lecture Notes in Computer Science  
Future Plans Although focused on checker generation for functional testing and coverage analysis, we view FoCs as a step towards a full methodology of "Formal Specification, Design and Verification".  ...  The number of VHDL lines in the resulting VHDL checker is at most quadratic in the size of the property.  ... 
doi:10.1007/10722167_40 fatcat:oz77fmee5rbszbdnx6trd66mty

Design-flow and synthesis for ASICs

Massimo Bombana, Patrizia Cavalloro, Salvatore Conigliaro, Roger B. Hughes, Gerry Musgrave, Giuseppe Zaza
1995 Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95  
The resulting design methodology combining both formal and more traditional design tools has been tested on a complex device in the area of telecommunications.  ...  phases of the design flow.  ...  in view of the improvement of the quality of the design cycle.  ... 
doi:10.1145/217474.217544 dblp:conf/dac/BombanaCCHMZ95 fatcat:iovpvob7d5hvpczrikhgaatmna

Design-Flow and Synthesis for ASICs: A Case Study

Massimo Bombana
1995 Proceedings - Design Automation Conference  
The resulting design methodology combining both formal and more traditional design tools has been tested on a complex device in the area of telecommunications.  ...  phases of the design flow.  ...  in view of the improvement of the quality of the design cycle.  ... 
doi:10.1109/dac.1995.249962 fatcat:5ulddl4rrraqpgz5wleeb5o6du

Co-synthesis and co-simulation of control-dominated embedded systems

Alessandro Balboni, William Fornaciari, Donatella Sciuto
1996 Design automation for embedded systems  
The proposed methodology is oriented towards the application field of controldominated embedded systems implemented onto a single chip.  ...  This paper presents a methodology for hardware/software co-design with particular emphasis on the problems related to the concurrent simulation and synthesis of hardware and software parts of the overall  ...  This research work tends to unify embedded system co-design and distributed systems design within a common conceptual framework.  ... 
doi:10.1007/bf00133305 fatcat:i5yb6xbdyfevrfd4hqudpjxbv4

The role of VHDL in the MCC CAD system

R.D. Acosta, M. Alexandre, G. Inken, B. Read
25th ACM/IEEE, Design Automation Conference.Proceedings 1988.  
The VHSIC Hardware Description Language (VHDL), currently undergoing standardization by the IEEE, supports the hierarchical design, documentation, and simulation of a wide range of digital system abstractions  ...  This paper describes a suite of utilities for manipulating VHDL designs that has been developed and integrated into the CAD System of the Microelectronics and Computer Technology Corporation (MCC).  ...  The authors would like to acknowledge the contributions of the following members of the MCC CAD Program to the development of the VHDL utilities and other parts of the CAD System discussed in this paper  ... 
doi:10.1109/dac.1988.14731 fatcat:odrlxxs3xrhd3cug2iwqz4ybge

System design utilizing integrated specification and performance models

A. Sarkar, R. Waxman, J.P. Cohoon
Proceedings of VHDL International Users Forum  
in a synergistic mannel: Such an integration enables a novel design methodology that makes speciJication modeling an integral part of the design process. 90 0-8186-6215-8/94 $03.00 0 1994 IEEE  ...  In this papel; we discuss bringing two early stages of digital system design --operational specijcation modeling and pelformance modeling-under the same simulation environment.  ...  ., and Barry Johnson at U.Va. for their suggestions and various contributions in the field of digital system design.  ... 
doi:10.1109/viuf.1994.323961 fatcat:ag3othjzxbb6jejx6fdxbjqlzy

Integrating the teaching of computer organization and architecture with digital hardware design early in undergraduate courses

N.L.V. Calazans, F.G. Moraes
2001 IEEE Transactions on Education  
First, to provide a better insight into the practical aspects of computer organization and architecture.  ...  This paper describes a new way to teach computer organization and architecture concepts with exte hands-on hardware design experience very early in Computer Science curricula.  ...  ACKNOWLEDGEMENTS The authors would like to acknowledge the continued support of Xilinx, Inc., through its University Prog Aldec, Inc. has provided the authors with two years of free licenses of its VHDL  ... 
doi:10.1109/13.925805 fatcat:lzhib3qbtbcrbnkqd3hiz4tama

ReconOS: An Operating System Approach for Reconfigurable Computing

Andreas Agne, Markus Happe, Ariane Keller, Enno Lubbers, Bernhard Plattner, Marco Platzner, Christian Plessl
2014 IEEE Micro  
The ReconOS operating system, programming model, and system architecture offers unified OS services for functions executing in software and hardware and a standardized interface for integrating custom  ...  of applications between different reconfigurable computing systems.  ...  Version 3, which was released in early 2013, is a major overhaul that streamlines the hardware architecture toward a more lightweight and modular design.  ... 
doi:10.1109/mm.2013.110 fatcat:k5pk2ntw2zfypi4x7zait2x4lm
« Previous Showing results 1 — 15 out of 978 results