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An Extensible Secure OS Architecture for Embedded Systems

Ning Li, Yuki Kinebuchi, Hiromasa Shimada, Tatsuo Nakajima
2013 Journal of Information Processing  
Basis of big local memory space that is unsuitable for embedded systems.  ...  In order to generalize this architecture, we adopt a secure pager to extend the local memory space (physically small) virtually by a swap mechanism with integrity checking of the monitoring service.  ...  Since we focus on applying our architecture to embedded systems, maybe real-time systems, it is better to use a monitoring service with the passive pattern to reduce the overhead of the guest OS.  ... 
doi:10.2197/ipsjjip.21.650 fatcat:k3acmz6qonfxzb7exuz3iuoca4

Compiler-Assisted Memory Encryption for Embedded Processors [chapter]

Vijay Nagarajan, Rajiv Gupta, Arvind Krishnaswamy
2009 Lecture Notes in Computer Science  
In this paper we present a compilerassisted strategy that uses minimal hardware support to reduce the overhead of memory encryption in low-to medium-end embedded processors.  ...  Our experiments show that the proposed technique reduces average execution time overhead of memory encryption for low-end (medium-end) embedded processor with 0 KB (32 KB) L1 cache from 60% (13.1%), with  ...  In section 2 we review how encryption/decryption is performed and motivate this work by showing the high overhead of memory encryption for low-and medium-end embedded processors.  ... 
doi:10.1007/978-3-642-00904-4_3 fatcat:zt7euil7jzeixbgete5zx3xpyu

Compiler-Assisted Memory Encryption for Embedded Processors [chapter]

Vijay Nagarajan, Rajiv Gupta, Arvind Krishnaswamy
2007 Lecture Notes in Computer Science  
In this paper we present a compilerassisted strategy that uses minimal hardware support to reduce the overhead of memory encryption in low-to medium-end embedded processors.  ...  Our experiments show that the proposed technique reduces average execution time overhead of memory encryption for low-end (medium-end) embedded processor with 0 KB (32 KB) L1 cache from 60% (13.1%), with  ...  In section 2 we review how encryption/decryption is performed and motivate this work by showing the high overhead of memory encryption for low-and medium-end embedded processors.  ... 
doi:10.1007/978-3-540-69338-3_2 fatcat:iyz7a3tyirbyvavibiskz4fpwy

Configurable memory security in embedded systems

Jérémie Crenne, Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet, Russell Tessier, Deepak Unnikrishnan
2013 ACM Transactions on Embedded Computing Systems  
The benefits of our low overhead memory protection approaches are demonstrated using four applications implemented in a field-programmable gate array (FPGA) in an embedded system prototyping platform.  ...  The lightweight circuitry included to support application loading from flash memory adds about 10% FPGA area overhead to the processor-based system and main memory security hardware.  ...  Our security core and associated memory was implemented in FPGA logic and embedded memory and interfaced to the processor via a 32-bit processor local bus (PLB).  ... 
doi:10.1145/2442116.2442121 fatcat:nonibdp57jh57lsb7uda7ntdte

High-Efficiency Parallel Cryptographic Accelerator for Real-Time Guaranteeing Dynamic Data Security in Embedded Systems

Zhun Zhang, Xiang Wang, Qiang Hao, Dongdong Xu, Jinlei Zhang, Jiakang Liu, Jinhui Ma
2021 Micromachines  
In particular, the data exchanges in embedded Systems-on-Chip (SoCs) using main memory are exposing many security vulnerabilities to external attacks, which will cause confidential information leakages  ...  cryptographic accelerator does not incur significant performance overhead on providing confidentiality and integrity protections for exchanged data; its average performance overhead reduces to as low as  ...  in a performance overhead to processor.  ... 
doi:10.3390/mi12050560 pmid:34063441 fatcat:o6e4zpjoure6tcx245jzah6wgq

Hardware support for code integrity in embedded processors

Milena Milenković, Aleksandar Milenković, Emil Jovanov
2005 Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems - CASES '05  
Moreover, as capabilities of embedded processors increase, the applications running on these systems also grow in size and complexity, and so does the number of security vulnerabilities.  ...  This paper proposes four new architectural extensions to ensure complete run-time code integrity using instruction block signature verification.  ...  This is a frequent case in embedded processor caches, for example in Intel's Xscale processor [2] .  ... 
doi:10.1145/1086297.1086306 dblp:conf/cases/MilenkovicMJ05 fatcat:4dmbalorwrfz7i2iluczlwdvju

Memory encryption

Michael Henson, Stephen Taylor
2014 ACM Computing Surveys  
Memory encryption has yet to be used at the core of operating system designs to provide confidentiality of code and data.  ...  This approach has provided insights into the use of encryption but has involved unacceptable overheads and has not been adopted in commercial operating systems.  ...  Prefetching uses stream buffers to capture spatial locality in programs by copying additional contiguous blocks of memory into local cache after each miss.  ... 
doi:10.1145/2566673 fatcat:jmnwf76mm5calh5vjqh4ukchju

Using instruction block signatures to counter code injection attacks

Milena Milenković, Aleksandar Milenković, Emil Jovanov
2005 SIGARCH Computer Architecture News  
The coefficients of the MISR and the key used for signature encryption are based on a hidden processor key.  ...  Signatures are generated during a trusted installation process, using a multiple input signature register (MISR), and stored in an encrypted form.  ...  Due to the everincreasing processor-memory speed gap, the memory access overhead will be the predominant overhead component.  ... 
doi:10.1145/1055626.1055641 fatcat:uazx2ahuwrdjlbi7heap46gdhq

Defending Against Attacks on Main Memory Persistence

William Enck, Kevin Butler, Thomas Richardson, Patrick McDaniel, Adam Smith
2008 2008 Annual Computer Security Applications Conference (ACSAC)  
The MECU encrypts all memory transfers between the processor-local level 2 cache and main memory to ensure plaintext data is never written to the persistent medium.  ...  Main memory persistence will soon be the norm as recent advancements in MRAM and FeRAM position non-volatile memory technologies for widespread deployment in laptop, desktop, and embedded system main memory  ...  The MECU uses a write buffer to mask both the encryption and memory delay, similar to methods of reducing write latencies in write-through caches.  ... 
doi:10.1109/acsac.2008.45 dblp:conf/acsac/EnckBRMS08 fatcat:ezrbjqm6sbgbxksu3i4hqecluu

Architectural support for securing application data in embedded systems

Olga Gelbart, Eugen Leontie, Bhagirath Narahari, Rahul Simha
2008 2008 IEEE International Conference on Electro/Information Technology  
Encrypted execution and data (EED) platforms, where instructions and data are stored in encrypted form in memory, while incurring overheads of encryption have proven to be attractive because they offer  ...  In this paper we present an architectural approach to address a class of memory spoofing attacks, in which an attacker can control the address bus and spoof memory blocks as they are loaded into the processor  ...  Although hard to replicate a forged exact value inside an encrypted block without knowing the encryption key, brute force can lead to approximate values in reasonable times, thus tricking the running application  ... 
doi:10.1109/eit.2008.4554261 dblp:conf/eit/GelbartLNS08 fatcat:dvalfepaerdptn4qh72l36enie

Hardware-Assisted Security Monitoring Unit for Real-Time Ensuring Secure Instruction Execution and Data Processing in Embedded Systems

Xiang Wang, Zhun Zhang, Qiang Hao, Dongdong Xu, Jiqing Wang, Haoyu Jia, Zhiyu Zhou
2021 Micromachines  
to a significant speed degradation to processor while executing different benchmarks, and its average performance overhead reduces to 2.18% on typical 8-KB I/D-Caches.  ...  The hardware security of embedded systems is raising more and more concerns in numerous safety-critical applications, such as in the automotive, aerospace, avionic, and railway systems.  ...  Performance Overhead HAM [  ... 
doi:10.3390/mi12121450 pmid:34945300 pmcid:PMC8708534 fatcat:ph7h7vlqezdyddlowxvh5ueae4

Transparent code authentication at the processor level

A.O. Durahim, E. Savaş, B. Sunar, T.B. Pedersen, Ö. Kocabaş
2009 IET Computers & Digital Techniques  
In addition, the proposed authentication method supports seamless encryption of code (and static data).  ...  The technique we propose tightly integrates the authentication mechanism into the processor core.  ...  Acknowledgement The authors would like to thank the anonymous referees for their helpful comments.  ... 
doi:10.1049/iet-cdt.2007.0122 fatcat:yzgxjqyqwvbr7lcs7o3fbsxvpm

Aegis: A single-chip secure processor

G. Suh, Charles O'Donnell, Srinivas Devadas
2007 IEEE Design & Test of Computers  
Memory encryption and integrity verification mechanisms guarantee the privacy and the integrity of off-chip memory content, respectively.  ...  This thesis also shows that using AEGIS requires only minor modifications to traditional operating systems and compilers.  ...  There are a few ways to reduce this memory overhead.  ... 
doi:10.1109/mdt.2007.4343587 fatcat:qzwlnqrklvat5kgjzia7yed47q

Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution

N.R. Potlapally, S. Ravi, A. Raghunathan, R.B. Lee, N.K. Jha
2007 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
A promising approach for improving performance in embedded systems is to use application-specific instruction set processors that are designed based on configurable and extensible processors.  ...  as instruction and data cache sizes, processor-memory interface width, write buffers, etc., and (b) extending the base instruction set of the processor using custom instructions for both cryptographic  ...  part, in a costeffective manner on an embedded processor.  ... 
doi:10.1109/tvlsi.2007.896912 fatcat:du7oue3javbtvfcaphgo5lbj5i

Implementation and Analysis of Optimized AES on FPGA

Nikita Purohit, Meghana A.
2017 International Journal of Computer Applications  
Optimized AES is implemented using softcore processor on FPGA Spartan-6 kit and the results are obtained using timing analyzer tool of Xilinx design suite 14.5.  ...  In today's world of digital transmission and reception of data and images high performance processing hardware is required.  ...  BRAM, data local memory bus(dlmb) controller and instruction local memory bus is included while in slave processor peripherals like xps timer, xps_UART, quad_SPI are included as shown in Fig.3 Fig  ... 
doi:10.5120/ijca2017914899 fatcat:4lqkrilt6veu7oayxynxownwp4
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