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Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors
2007
International Symposium on Code Generation and Optimization (CGO'07)
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Dynamic predication has been proposed to reduce the branch misprediction penalty due to hard-to-predict branch instructions. ...
DMP requires significant support from a profiling compiler to determine which branch instructions and control-flow structures can be dynamically predicated. ...
[2] proposed a framework that considers branch misprediction rate and instruction scheduling effects due to predication in an EPIC processor to decide which branches would not benefit from if-conversion ...
doi:10.1109/cgo.2007.31
dblp:conf/cgo/KimJMP07
fatcat:hzg23256qfdsnhoml4zeu6hf5u
Reducing the Branch Power Cost in Embedded Processors Through Static Scheduling, Profiling and SuperBlock Formation
[chapter]
2006
Lecture Notes in Computer Science
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We describe a method of reducing dynamic predictor power dissipation without degrading prediction accuracy by using a combination of local delay region scheduling and run time profiling of branches. ...
Recent research indicates that the power cost of a large dynamic branch predictor is offset by the power savings created by its increased accuracy. ...
In this paper we explore the use of delay region scheduling, branch profiling and hint bits (in conjunction with a dynamic predictor) in order to reduce the branch power cost for mobile devices, without ...
doi:10.1007/11859802_31
fatcat:yl4homyrvjgapezd55i2cyyuqm
Towards an energy efficient branch prediction scheme using profiling, adaptive bias measurement and delay region scheduling
2007
2007 International Conference on Design & Technology of Integrated Systems in Nanoscale Era
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This power cost is proportional to the number of accesses made to that dynamic predictor during a program's execution. ...
We show that, with the combined use of these two methods, the number of dynamic branch predictor accesses/updates can be reduced by up to 62%. ...
Even though a dynamic predictor uses a great deal of power, the increased prediction accuracy and improved processor performance it provides results in power saving by the reduced number of branch mispredictions ...
doi:10.1109/dtis.2007.4449485
fatcat:ndp3424zp5cddc4vlzrcmijl3y
Interaction cost and shotgun profiling
2004
ACM Transactions on Architecture and Code Optimization (TACO)
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Second, we illustrate the value of using interaction costs in processor design and optimization. ...
In this paper, we introduce a new model for understanding event costs to facilitate processor design and optimization. ...
ACKNOWLEDGMENTS We thank Mary Vernon, David Wood, and Amir Roth for contributions to this work. ...
doi:10.1145/1022969.1022971
fatcat:dy55yxautrcppku6s6c4tg4jru
Improving the performance of object-oriented languages with dynamic predication of indirect jumps
2008
SIGARCH Computer Architecture News
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branch target buffer based predictor, while also reducing energy consumption by 24.8%. ...
If the jump would actually have been mispredicted, its dynamic predication eliminates a pipeline flush, thereby improving performance. ...
We also acknowledge the Texas Advanced Computing Center (TACC) at The University of Texas at Austin for providing HPC resources that have contributed to the research results reported within this paper. ...
doi:10.1145/1353534.1346293
fatcat:bq63wny46fb3dpepyevtstlyte
Improving the performance of object-oriented languages with dynamic predication of indirect jumps
2008
SIGPLAN notices
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branch target buffer based predictor, while also reducing energy consumption by 24.8%. ...
If the jump would actually have been mispredicted, its dynamic predication eliminates a pipeline flush, thereby improving performance. ...
We also acknowledge the Texas Advanced Computing Center (TACC) at The University of Texas at Austin for providing HPC resources that have contributed to the research results reported within this paper. ...
doi:10.1145/1353536.1346293
fatcat:xk5kumpxgjg5hebooawabvheja
Improving the performance of object-oriented languages with dynamic predication of indirect jumps
2008
ACM SIGOPS Operating Systems Review
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branch target buffer based predictor, while also reducing energy consumption by 24.8%. ...
If the jump would actually have been mispredicted, its dynamic predication eliminates a pipeline flush, thereby improving performance. ...
We also acknowledge the Texas Advanced Computing Center (TACC) at The University of Texas at Austin for providing HPC resources that have contributed to the research results reported within this paper. ...
doi:10.1145/1353535.1346293
fatcat:rf53ooj2xvervj7fmbeffrxdgu
Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths
2006
Microarchitecture (MICRO), Proceedings of the Annual International Symposium on
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The goal of this paradigm is to eliminate branch mispredictions due to hard-to-predict dynamic branches by dynamically predicating them without requiring ISA support for predicate registers and predicated ...
To achieve this without incurring large hardware cost and complexity, the compiler provides control-flow information by hints and the processor dynamically predicates instructions only on frequently executed ...
Acknowledgments Special thanks to Chang Joo Lee for the support he provided in power modeling. ...
doi:10.1109/micro.2006.20
dblp:conf/micro/KimJMP06
fatcat:5lhl3osqafbj7ic3zcoi6zytnu
Wish Branches: Enabling Adaptive and Aggressive Predicated Execution
2006
IEEE Micro
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The compiler decides to keep a branch as a conditional branch or to predicate it based on compiletime profile information. ...
A predicated branch remains predicated for all its dynamic instances even if it turns out to be very easy to predict at runtime. ...
In contrast, if the compiler converts such a branch to a wish branch, the old binary's performance would not degrade on the new processor, since the new processor can dynamically decide not to use predicated ...
doi:10.1109/mm.2006.27
fatcat:xt4tpnx6b5djdj2qgoyqeypc5m
Compiler controlled value prediction using branch predictor based confidence
2000
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture - MICRO 33
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A new branch instruction that ignores innocuous value mispredictions is shown to eliminate unnecessary mispredictions when program semantics aren't violated by confidence branch mispredictions. ...
The branch predictor is used to estimate the confidence of the value predictor for speculated instructions. ...
Acknowledgements We would like to thank the anonymous reviewers for their valuable comments. This material is based upon work supported under a National Science Foundation Graduate Fellowship. ...
doi:10.1145/360128.360164
fatcat:y4eclwpbcvampmrqjvjilmp4q4
Per-thread cycle accounting in SMT processors
2009
SIGARCH Computer Architecture News
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are running simultaneously on the SMT processor. ...
For one, the estimated single-thread alone execution time provides an accurate picture to system software of the actually consumed processor cycles per thread. ...
Acknowledgments The authors would like to thank the anonymous reviewers for their valuable comments and suggestions. ...
doi:10.1145/2528521.1508260
fatcat:qir3y4cob5dp5crixlaebpr2vq
Per-thread cycle accounting in SMT processors
2009
Proceeding of the 14th international conference on Architectural support for programming languages and operating systems - ASPLOS '09
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are running simultaneously on the SMT processor. ...
For one, the estimated single-thread alone execution time provides an accurate picture to system software of the actually consumed processor cycles per thread. ...
Acknowledgments The authors would like to thank the anonymous reviewers for their valuable comments and suggestions. ...
doi:10.1145/1508244.1508260
dblp:conf/asplos/EyermanE09
fatcat:rl632osjnzgmxoxt6pmtditfs4
Per-thread cycle accounting in SMT processors
2009
SIGPLAN notices
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are running simultaneously on the SMT processor. ...
For one, the estimated single-thread alone execution time provides an accurate picture to system software of the actually consumed processor cycles per thread. ...
Acknowledgments The authors would like to thank the anonymous reviewers for their valuable comments and suggestions. ...
doi:10.1145/1508284.1508260
fatcat:jkzumnjppnehhfzspsilz6isf4
Reducing indirect function call overhead in C++ programs
1994
Proceedings of the 21st ACM SIGPLAN-SIGACT symposium on Principles of programming languages - POPL '94
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We examine the improvement offered by compile-time optimization and static and dynamic prediction techniques, and demonstrate how compilers can use existing branch prediction mechanisms to improve performance ...
Using these methods with the programs we examined, the number of instructions between mispredicted breaks in control can be doubled on existing computers. ...
Acknowledgements We would like to thank Ben Zorn, John Feehrer and the reviewers for comments on the paper. ...
doi:10.1145/174675.177973
dblp:conf/popl/CalderG94
fatcat:bthshjuepzewzinddpt37f7xny
CVP
2012
Proceedings of the 26th ACM international conference on Supercomputing - ICS '12
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However, previous indirect branch predictors either require a significant amount of hardware storage and complexity, or heavily rely on the expensive manual profiling. ...
The compiler-identified information is then fed back to the dynamic predictor and is further used to hint the indirect branch prediction at runtime. ...
However, CVP prediction can significantly reduce the indirect branch MPKI by 74% (from 3.98 to 1.05). As a result, CVP prediction still significantly reduces the total branch mispredictions. ...
doi:10.1145/2304576.2304593
dblp:conf/ics/TanLTC12
fatcat:wwnlvk3burfrdd34amejyhucg4
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