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Using a high-performance, programmable secure coprocessor
[chapter]
1998
Lecture Notes in Computer Science
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These obstacles motivate building a high-performance secure coprocessor that balances security with easy third-party programmability|but these obstacles also provide many design challenges. ...
High-performance secure coprocessors can address these threats. However, using this technology for practical security solutions requires overcoming numerous technical and business obstacles. ...
Suresh Chari, Joan Dyer, Gideon Eisenstadter, Bob Gezelter, Juan Gonzalez, Je Kravitz, Mark Lindemann, Joe McArthur, Dennis Nagel, Ron Perez, Pankaj Rohatgi, David Toll, and Bennet Yee; the IBM Global Security ...
doi:10.1007/bfb0055474
fatcat:nf2yri2nr5ddvkdiukzxeh5rma
Architectural design features of a programmable high throughput AES coprocessor
2004
International Conference on Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004.
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Programmable, high throughput domain specific crypto processors are required for different networking applications. ...
This paper presents the architectural design features that lead to a multiple Gbits/s rate AES coprocessor, which is programmable with domain specific instructions for Gbit throughput IPSec and other applications ...
These techniques help us to design a high-throughput crypto coprocessor, which is programmable with a domain specific instruction set. ...
doi:10.1109/itcc.2004.1286703
dblp:conf/itcc/HodjatSV04
fatcat:dshi4k2jqzgwjkwovoy5bimrx4
High-throughput programmable cryptocoprocessor
2004
IEEE Micro
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Combining programmability with high throughput supports a wide range of current and future standards for security applications. A high-speed CPU is one way to implement security primitives. ...
High-speed Internet Protocol security (IPsec) applications require high throughput and flexible security engines. ...
Combining programmability with high throughput supports a wide range of current and future standards for security applications. A high-speed CPU is one way to implement security primitives. ...
doi:10.1109/mm.2004.11
fatcat:z46xetlq2re65hojayvlm3daoa
A Side-channel Attack Resistant Programmable PKC Coprocessor for Embedded Applications
2007
2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation
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This paper describes the design of a programmable coprocessor for Public Key Cryptography (PKC) on an FPGA. ...
This makes the coprocessor very flexible and particularly suitable to be used in embedded environments where the border between hardware and software needs to be decided depending on the application. ...
When very high performance is required or when a high volume of coprocessors is needed, ASICs are chosen as implementation platforms. ...
doi:10.1109/icsamos.2007.4285751
dblp:conf/samos/MentensSBPV07
fatcat:el7kpbazm5artht3626yph7zkq
The IBM PCIXCC: A new cryptographic coprocessor for the IBM eServer
2004
IBM Journal of Research and Development
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This paper describes the PCIXCC, the new coprocessor introduced in the IBM z990 server. In many ways, PCIXCC is a watershed design. ...
It offers the performance demanded by today s Web servers, it supports the complex and specialized cryptographic functions needed in the banking and finance industry, and it uses packaging technology that ...
**Trademark or service mark of Intel Corporation or its subsidiaries, Linus Torvalds, Atmel Corporation, Europay International, MasterCard International Incorporated, Visa International, or SET Secure ...
doi:10.1147/rd.483.0475
fatcat:5j64tgvjrfekthkazks22fcxnu
Programmable and Parallel ECC Coprocessor Architecture: Tradeoffs between Area, Speed and Security
[chapter]
2009
Lecture Notes in Computer Science
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The programmable design of the coprocessor enables tradeoffs between area, speed, and security. ...
In this paper, we describe a generic ECC coprocessor architecture, which is scalable and programmable. ...
The use of PicoBlaze as a new control hierarchy was first proposed in [29] and based on that we in [30] proposed a Dual-PicoBlaze based design to achieve a high instruction rate of 1 instruction per ...
doi:10.1007/978-3-642-04138-9_21
fatcat:crj6f5vw55hwrhy6yqu3nznz7u
Towards a hardware-assisted information flow tracking ecosystem for ARM processors
2016
2016 26th International Conference on Field Programmable Logic and Applications (FPL)
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This work details a hardware-assisted approach for information flow tracking implemented on reconfigurable chips. ...
INTRODUCTION Nowadays, high-technology systems are highly threatened by security issues. ...
Next steps are to build a full-featured system including a secure DIFT coprocessor. Then, DIFT on both Cortex-A9 cores will be implemented by duplicating DIFT coprocessor and other IPs. ...
doi:10.1109/fpl.2016.7577396
dblp:conf/fpl/WahabCAHLG16
fatcat:4e4howgbvbej3hoqmsbtmn64pu
An overview of security issues in cluster interconnects
2006
Sixth IEEE International Symposium on Cluster Computing and the Grid (CCGRID'06)
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Widespread use of cluster systems in diverse set of applications has spurred significant interest in providing high performance cluster interconnects. ...
secure coprocessor and the Network Interface Card (NIC) by illustrating its challenges in doing so. ...
Among several reasons, a high CPU overhead has been a major hurdle for Ethernet to be used in such high performance communication environment. ...
doi:10.1109/ccgrid.2006.1630920
fatcat:iyybq4xx6vhrbnpnyit5w3lgmu
Anatomy of a portable digital mediaprocessor
2004
IEEE Micro
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Some programmable solutions 1,2 offer competitive performance on several video and audio tasks but lack still-image processing performance and do not integrate a majority of the imaging/video subsystem ...
A typical GPP's cost runs from the low hundreds to the high hundreds of dollars, while a portable mediaprocessor will likely cost between five and 15 dollars. ...
Coprocessor subsystem The DM310's high performance and flexibility derive from the DSP core and the programmable coprocessors. The three coprocessors can operate at 144 MHz-twice the DSP clock speed. ...
doi:10.1109/mm.2004.1289289
fatcat:tb3sqvtkxnewda5joz754onwdu
Fpga-Oriented Secure Data Path Design: Implementation of a Public Key Coprocessor
2006
2006 International Conference on Field Programmable Logic and Applications
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Although this is a very low-cost FPGA, the performance results of our implementation meet the requirements of a broad range of high-end applications. ...
This paper introduces a secure FPGA implementation of a coprocessor for public key cryptography. It supports Elliptic Curve Cryptography (ECC) as well as the older RSA standard. ...
For some systems a general purpose microprocessor suffices the requirements, but when high performance is the main criterium, cryptographic coprocessors in hardware are indispensable. ...
doi:10.1109/fpl.2006.311205
dblp:conf/fpl/MentensSBVP06
fatcat:fhw4szm75ranpit2mebsiawmmu
A 1.96mm2 low-latency multi-mode crypto-coprocessor for PKC-based IoT security protocols
2015
2015 IEEE International Symposium on Circuits and Systems (ISCAS)
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In this paper, we present the implementation of a multi-mode crypto-coprocessor, which can support three different public-key cryptography (PKC) engines (NTRU, TTS, Pairing) used in post-quantum and identity-based ...
In this work, we propose the first-of-its-kind tri-mode PKC coprocessor for secured data transmission in Internet-of-Things (IoT) systems. ...
In other words, we use limited resource to achieve remarkable performance improvement.
Low Latency and Programmable Crypto-Coprocessor
V. ...
doi:10.1109/iscas.2015.7168763
dblp:conf/iscas/TsaiHSWC15
fatcat:hvtjfs2d4fbsrhk6lcsghsgp4a
WLAN security processor
2006
IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications
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It is designed to offload security encapsulation processing from the host microprocessor in an IEEE 802.11i compliant medium access control layer to a programmable hardware accelerator. ...
A novel wireless local area network (WLAN) security processor is described in this paper. ...
and high throughput of hardware encryption coprocessors. ...
doi:10.1109/tcsi.2006.877888
fatcat:2gvkvjp4izardgdi46evsadr2e
Decoupling Dynamic Information Flow Tracking with a dedicated coprocessor
2009
2009 IEEE/IFIP International Conference on Dependable Systems & Networks
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Using a full-system hardware prototype and realistic Linux workloads, we show that the DIFT coprocessor provides the same security guarantees as current DIFT architectures with low runtime overheads. ...
The coprocessor is a small hardware engine that performs logical operations and caches 4-bit tags. ...
This work was supported by an Intel Foundation Graduate Fellowship, a Stanford Graduate Fellowship funded by Sequoia Capital, and NSF awards CCF-0701607 and CCF-0546060. ...
doi:10.1109/dsn.2009.5270347
dblp:conf/dsn/KannanDK09
fatcat:ktij6xxfgfbblizczaoaqmsztq
Architectures of flexible symmetric key crypto engines—a survey
2013
ACM Computing Surveys
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In particular, key management security (e.g., secure key generation and transmission, the use of a hierarchical key structure composed of session keys and master keys) has frequently been neglected to ...
the benefit of performance and/or flexibility. ...
Based on the single AES-THETIC coprocessor [Su et al. 2005 ] the authors propose a high-performance multicore architecture, in which independent data paths for each AESTHETIC coprocessor allow multigigabit ...
doi:10.1145/2501654.2501655
fatcat:h5pccigb35hfvinkrpn7s75gl4
Platform-based design for an embedded-fingerprint-authentication device
2005
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The formulation of a platform as a VM enables design exploration and incremental design validation throughout the design traject, and results in a specialized, but still programmable, platform. ...
an field programmable gate array. ...
The use of hardware encryption is done not only for performance, but also for reasons of security. ...
doi:10.1109/tcad.2005.853709
fatcat:vzvdcwfiv5givjupbct2pmq5cq
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