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An improved algorithm for the automatic verification of finite state systems using temporal logic

Michael C. Browne
2018
Every atomic proposition The Finite State System Description The finite state systems that our algorithm deals with are 5-tuples, M = (S, /, O, R, P) where • S is a finite set of states. • / is a finite  ...  In order to remove these conditional transitions so that this algorithm can be used, it is necessary to replace each state of the original system by a set of states, one for each possible combination of  ...  The difference in performance can be explained by the fact that most of the formulas that we have attempted to verify in practice belong to a special class for which the complexity of the new algorithm  ... 
doi:10.1184/r1/6603317.v1 fatcat:jyxi2kaoorhcbhyatod6yrap2m

Limits for automatic verification of finite-state concurrent systems

Krzysztof R. Apt, Dexter C. Kozen
1986 Information Processing Letters  
For example, automatic verification of correctness of the alternating bit protocol on the system of [2] took just over 19 seconds of CPU time.  ...  To check correctness of such a solution using the systems of [1,2,4] (provided, for each n ;;;,: 2, the solution uses only a finite number of states), one would have to verify the solutions for 2 processes  ... 
doi:10.1016/0020-0190(86)90071-2 fatcat:2a62wkz7ovfs7asptqbwky4cge

STeP: Deductive-algorithmic verification of reactive and real-time systems [chapter]

Nikolaj Bjørner, Anca Browne, Eddie Chang, Michael Colón, Arjun Kapur, Zohar Manna, Henny B. Sipma, Tomás E. Uribe
1996 Lecture Notes in Computer Science  
STeP uses verification rules, verification diagrams, automatically generated invariants, model checking, and a collection of decision procedures to verify finite-and infinite-state systems.  ...  Verification rules are used to reduce temporal properties of systems to first-order verification conditions [8] .  ...  the validity of first-order and terriporal-logic formulas that are not proved automatically; and the Verification Diagram Editor, for the creation of Verification Diagrams.  ... 
doi:10.1007/3-540-61474-5_92 fatcat:4bak2upg5ncz7eb3iratmwbsom

Automatic verification of multi-agent systems security properties specified with LTL

Kholud Alghamdi, Marius Silaghi
2022 Proceedings of the ... International Florida Artificial Intelligence Research Society Conference  
We propose a way to verify security requirements of critical multi-agent system processes by using logic representationsand automatic reasoning.  ...  We show a model of such security requirements by using system liveness properties, and exemplify their verification on a real system that we implement for this purpose.  ...  Linear Temporal Logic A logic system commonly used to reason with complex dynamic systems is the Linear Temporal Logic (LTL) (Rescher and Urquhart 1971; Francez and Pnueli 1978; Rozier 2011) .  ... 
doi:10.32473/flairs.v35i.130551 fatcat:vphuii6oxvhktkmj7nnv6yehsu

Page 5384 of Mathematical Reviews Vol. , Issue 94i [page]

1994 Mathematical Reviews  
94i:68186 ders to improve automatic verification methods (extended abstract) (176-185). Susanne Graf and Bernhard Steffen, Compositional minimiza- tion of finite state systems (186-196); A.  ...  Krishnakumar, Reachability and recurrence in extended finite state machines: modular vector addition systems (110-122); June- Kyung Rho and Fabio Somenzi, Automatic generation of network invariants for  ... 

On The Integration of Decision Diagrams in High Order Logic Based Theorem Provers:a Survey

Sa'ed Abed, Otmane Ait Mohamed, Ghiath Al Sammane
2007 Journal of Computer Science  
The paper also tries to answer which is the best decision graphs formalization for theorem provers as what is the optimized set of operations to efficiently manipulate the decision graphs inside theorem  ...  This survey discuss approaches that integrate Decision Diagrams inside High Order Logic based Theorem provers.  ...  Thus, the verification of properties for finite-state systems is decidable. Much of this work is based on Binary Decision Diagrams [2] .  ... 
doi:10.3844/jcssp.2007.810.817 fatcat:gu5y5qe4azbpblxoebifj6ys5a

Page 2817 of Mathematical Reviews Vol. , Issue 93e [page]

1993 Mathematical Reviews  
Mirkowska (Pau) 93e:68074 68Q60 68Q10 Zhao, Xu Dong (PRC-HEF); Feng, Yu Lin (PRC-HEF) Automatic and hierarchical verification for concurrent systems. J. Comput. Sci. Tech.  ...  , Kiyoharu (J-KYOTE-]); Fujii, Hiroshi; Yajima, Shuzo (J-K YOTE-I) Regular temporal logic expressively equivalent to finite automata and its application to logic design verification.  ... 

Page 575 of Mathematical Reviews Vol. , Issue 2003A [page]

2003 Mathematical Reviews  
Automatic systems can be collapsed using Myhill-Nerode relations in much the same way that finite automata can.  ...  One can use this fact to solve certain infinite systems of inequalities over a Kleene algebra. Automatic systems are a special class of infinite systems that can be viewed as infinite-state automata.  ... 

A semantics driven temporal verification system [chapter]

G. D. Gough, H. Barringer
1988 Lecture Notes in Computer Science  
We present an overview of SMG, a generic state machine generator, which interfaces to various temporal logic model checkers and provides a practical generic temporal verification system.  ...  SMG transforms programs written in user-definable languages to suitable finite state models, thus enabling fast verification of temporal properties of the input program.  ...  Verification System Architecture We agree with the conclusions of [BC86,BCDM84,CES86] that the use of model checkers provides an attractive and tractable approach to automatic verification of temporal  ... 
doi:10.1007/3-540-19027-9_2 fatcat:okuk3f5cnzamtf7out7kqp25li

Page 3265 of Mathematical Reviews Vol. , Issue 87f [page]

1987 Mathematical Reviews  
P. (1-MA) Using temporal logic for automatic verification of finite state systems. Logics and models of concurrent systems (La Colle-sur-Loup, 1984), 3-26, NATO Adv. Sci. Inst. Ser. F: Comput.  ...  :68038; Clarke, Emer- son and Sistla, “Automatic verification of finite-state concurrent systems using temporal logic specifications”, Tenth ACM sympo- sium on principles of programming languages (Austin  ... 

Verification of Infinite State Systems [chapter]

Ahmed Bouajjani
2003 Lecture Notes in Computer Science  
During the two last decades, significant achievements have been obtained in the case of finite-state systems (systems with finitely many states).  ...  One of the main actual challenges in the domain of automated verification is the conception of methods and tools allowing to deal with verification problems beyond the finite-state framework.  ...  Can we use results developed for infinite-state verification to this special class of infinite-state systems?  ... 
doi:10.1007/978-3-540-45220-1_7 fatcat:4j5lzdbfc5hd7ptdo4tpwvmd2m

A brief account of runtime verification

Martin Leucker, Christian Schallhart
2009 The Journal of Logic and Algebraic Programming  
Finally, the use of runtime verification for contract enforcement is briefly pointed out.  ...  In this paper, a brief account of the field of runtime verification is given.  ...  Model checking, which is an automatic verification technique, is mainly applicable to finite-state systems.  ... 
doi:10.1016/j.jlap.2008.08.004 fatcat:6su22iv37rgvndrtaizimmgz6a

Distributed Mils (D-Mils) Specification, Analysis, Deployment, And Assurance Of Distributed Critical Systems

Harald Rueß, Stefano Tonetta
2015 International Conference on High Performance Embedded Architectures and Compilers  
Presentation on D-MILS project overview and verification framework  ...  : t Key idea: check if can be visited at most times for increasing value of t Reduced to invariant checking t Very efficient for finite-state systems t Integrated with IC3 for an incremental check  ...  of different n Implemented in nuXmv t Combined with IC3IA for verification of infinite-state systems K-liveness for timed/hybrid models n Problem for parametric and real-time/hybrid systems t The number  ... 
doi:10.5281/zenodo.47985 dblp:conf/hipeac/RuessT15 fatcat:ovbvzpwbarh5dmeckjxa3ru2e4

Automatic property generation for formal verification applied to HDL-based design of an on-board computer for space applications

Wesley Silva, Eduardo Bezerra, Markus Winterholer, Djones Lettnin
2013 2013 14th Latin American Test Workshop - LATW  
This work presents a new method for automatic property generation for formal verification of Hardware Description Language (HDL) based systems.  ...  Formal verification using model checking represents a system as formal model that are automatically generated by synthesis tools.  ...  The authors would like to thank also the Cadence Academic Network (CAN) for the tools licenses.  ... 
doi:10.1109/latw.2013.6562663 dblp:conf/latw/SilvaBWL13 fatcat:tnqsu36s4jeorhulhom72ypgta

Formal reasoning about dialogue properties with automatic support

Fabio Paterno'
1997 Interacting with computers  
We provide an example of a set of general user interfaces properties, and we show how these properties can be tailored for specific cases and thus be used as a framework to evaluate the design of the interactive  ...  This paper discusses the possibilities of verifying the properties of user interfaces and related problems, such as when the dialogue specification has an infinite number of states.  ...  Acknowledgements I wish to thank the anonymous reviewers for their comments which were useful for improving the presentation of the final version of the paper.  ... 
doi:10.1016/s0953-5438(97)00015-5 fatcat:jwwc27mdybd65c5achkq6rzrzi
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