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Using SAT for combinational equivalence checking

E.I. Goldberg, M.R. Prasad, R.K. Brayton
Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001  
This paper revisits the application of Satisfiability (SAT) algorithms to the combinational equivalence checking (CEC) problem.  ...  This paper addresses the problem of combinational equivalence checking (CEC) which forms one of the key components of the current verification methodology for digital systems.  ...  Acknowledgements We would like to thank Jerry Burch, Armin Biere, Andreas Kuehlmann and all the reviewers of this paper for useful discussions, feedback and comments.  ... 
doi:10.1109/date.2001.915010 dblp:conf/date/GoldbergPB01 fatcat:6zrypqcxnnev5jhcveuyjcrhdi

Language-driven Validation of Pipelined Processors using Satisfiability Solvers

Prabhat Mishra, Heon-mo Koo, Zhuo Huang
2005 International Workshop on Microprocessor Test and Verification  
This paper outlines our plan to address these challenges using satisfiability checking.  ...  This paper describes two practical challenges in this methodology: test generation and equivalence checking.  ...  Li-C Wang and Feng Lu of University of California, Santa Barbara for giving us the opportunity to use the Seq-SAT tool.  ... 
doi:10.1109/mtv.2005.14 dblp:conf/mtv/MishraKH05 fatcat:sdbfzkg23ngcjnyd34emg76gla

SAT and ATPG

Armin Biere, Wolfgang Kunz
2002 Computer-Aided Design (ICCAD), IEEE International Conference on  
In this survey, we outline basic SAT-and ATPG procedures as well as their applications in formal hardware verification.  ...  Application: combinational equivalence checking SAT and ATPG have proved to be important instruments in combinational equivalence checking.  ...  The task of combinational equivalence checking is to check whether or not two combinational circuits implement the same Boolean functions.  ... 
doi:10.1145/774572.774687 dblp:conf/iccad/BiereK02 fatcat:lwwiornxcjhtlfa2ffmwgnvoty

Combinational Equivalence Checking Using Incremental SAT Solving, Output Ordering, and Resets

Stefan Disch, Christoph Scholl
2007 2007 Asia and South Pacific Design Automation Conference  
In this paper we focus on SAT based equivalence checking making use of incremental SAT techniques which are well known from their application in Bounded Model Checking.  ...  Combinational equivalence checking is an essential task in circuit design.  ...  In this paper we will focus on SAT based combinational equivalence checking.  ... 
doi:10.1109/aspdac.2007.358110 dblp:conf/aspdac/DischS07 fatcat:whma5nslsvhljmcpenfmjdd34q

Combinational equivalence checking using satisfiability and recursive learning

João Marques-Silva, Thomas Glass
1999 Proceedings of the conference on Design, automation and test in Europe - DATE '99  
In this paper we study the application of Boolean Satisfiability (SAT) algorithms for solving the Combinational Equivalence Checking (CEC) problem.  ...  The problem of checking the equivalence of combinational circuits is of key significance in the verification of digital circuits.  ...  As a result, several approaches have been proposed for solving the Combinational Equivalence Checking (CEC) problem.  ... 
doi:10.1145/307418.307477 fatcat:x7lk4lt4unhqjm7ptpmpj5vrke

Fast Equivalence-checking for Quantum Circuits [article]

Shigeru Yamashita, Igor L. Markov
2013 arXiv   pre-print
We also combine existing quantum verification tools with the use of SAT-solvers.  ...  Experiments with circuits for Shor's number-factoring algorithm, containing thousands of gates, show improvements in efficiency by 3-4 orders of magnitude.  ...  By Step 7, properly-quantum gates are reduced, and we can use state-of-the-art SAT-based combinational equivalence-checking.  ... 
arXiv:0909.4119v3 fatcat:sjgkvmtyejgifmujovbxtg3rqa

EQUIPE: Parallel equivalence checking with GP-GPUs

Debapriya Chatterjee, Valeria Bertacco
2010 2010 IEEE International Conference on Computer Design  
Combinational equivalence checking (CEC) is a mainstream application in Electronic Design Automation used to determine the equivalence between two combinational netlists.  ...  In this work we propose EQUIPE, a novel combinational equivalence checking solution, which leverages the massive parallelism of modern general purpose graphic processing units.  ...  checking of the LDPC design, using one CPU-core for SAT solving.  ... 
doi:10.1109/iccd.2010.5647645 dblp:conf/iccd/ChatterjeeB10 fatcat:cwjgqls3fnd3poj6zfjyad2ybm

Fast equivalence-checking for quantum circuits

Shigeru Yamashita, Igor L. Markov
2010 2010 IEEE/ACM International Symposium on Nanoscale Architectures  
We also combine existing quantum verification tools with the use of SAT-solvers.  ...  For reversible circuits which arise as runtime bottlenecks of key quantum algorithms, we develop several verification techniques and empirically compare them.  ...  equivalence-checking tool for the conventional circuits.  ... 
doi:10.1109/nanoarch.2010.5510932 dblp:conf/nanoarch/YamashitaM10 fatcat:tlorcymoofbbbiwhgvf6ogxkfy

Equivalence Checking Using Trace Partitioning

Rajdeep Mukherjee, Daniel Kroening, Tom Melham, Mandayam Srivas
2015 2015 IEEE Computer Society Annual Symposium on VLSI  
We present experimental data quantifying the benefit of our partitioning method for both combinational and sequential equivalence checking of difficult arithmetic circuits and control-intensive circuits  ...  One application of equivalence checking is to establish correspondence between a high-level, abstract design and a low-level implementation.  ...  combinational equivalence checking for a 32-bit floating-point adder/subtractor for the case of addition C.  ... 
doi:10.1109/isvlsi.2015.110 dblp:conf/isvlsi/MukherjeeKMS15 fatcat:vexrgnkqsvg7fpj47nomdbvgom

SEChecker: A Sequential Equivalence Checking Framework Based on ${K}$th Invariants

Feng Lu, Kwang-Ting Cheng
2009 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Jointly, BMChecker and IChecker are used to compute the -th invariants, and are further integrated in a sequential circuit SAT solver for checking sequential equivalence.  ...  In this paper, we present a sequential equivalence checking framework based on a number of circuit-based SAT solving techniques as well as a novel invariant checker.  ...  For example, strong equivalent signals can be derived easily by checking combinational equivalences in the one-timeframe combinational model.  ... 
doi:10.1109/tvlsi.2008.2005311 fatcat:te6syf6sbnborjdr3mxm5saica

Robust Boolean reasoning for equivalence checking and functional property verification

A. Kuehlmann, V. Paruthi, F. Krohm, M.K. Ganai
2002 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
The presented reasoning technique was mainly developed for formal equivalence checking and property verification but can equally be used in other CAD applications.  ...  Many tasks in computer-aided design (CAD), such as equivalence checking, property checking, logic synthesis, and false paths analysis, require efficient Boolean reasoning for problems derived from circuits  ...  Fig. 27 illustrates the run times for the combined approach compared against an application of the SAT-solver alone. Again, the combined approach vastly outperforms the use of SAT alone. X.  ... 
doi:10.1109/tcad.2002.804386 fatcat:5q27lakt5bcu5oxupssranitei

SAT-based Automatic Rectification and Debugging of Combinational Circuits with LUT Insertions

Satoshi Jo, Takeshi Matsumoto, Masahiro Fujita
2014 IPSJ Transactions on System LSI Design Methodology  
Although this can be solved as SAT problem, we introduce to use commercial equivalence checker to improve the efficiency.  ...  In this paper, we present a rectification and debugging method for combinational circuits with LUTs by repeatedly applying Boolean SAT solvers.  ...  We can conclude that equivalence checker is more useful in our proposed method when circuits has more gates and more LUTs, compared to using SAT solvers for checking equivalence.  ... 
doi:10.2197/ipsjtsldm.7.46 fatcat:yqd4qlbnprb3lncoyyofb66hqa

SAT-Based Automatic Rectification and Debugging of Combinational Circuits with LUT Insertions

Satoshi Jo, Takeshi Matsumoto, Masahiro Fujita
2012 2012 IEEE 21st Asian Test Symposium  
Although this can be solved as SAT problem, we introduce to use commercial equivalence checker to improve the efficiency.  ...  In this paper, we present a rectification and debugging method for combinational circuits with LUTs by repeatedly applying Boolean SAT solvers.  ...  We can conclude that equivalence checker is more useful in our proposed method when circuits has more gates and more LUTs, compared to using SAT solvers for checking equivalence.  ... 
doi:10.1109/ats.2012.55 dblp:conf/ats/JoMF12 fatcat:azoowghn7naf7btwauk2dibmuq

SAT-Based Methods for Sequential Hardware Equivalence Verification without Synchronization

Zurab Khasidashvili, Ziyad Hanna
2003 Electronical Notes in Theoretical Computer Science  
The BDD-and SAT-based model checking and verification methods normally require an initial state.  ...  In this paper we propose a method allowing usage of SAT-based verification methods without a need for a user-given or a computed initial state.  ...  Wolfovitz for careful reading, and S.-Y. Huang and K.-T. Cheng for clarifying the subtleties of their ATPG method for checking 3-valued equivalence.  ... 
doi:10.1016/s1571-0661(05)82545-9 fatcat:awcmqqnxu5aqzgbs4tcmncvf3u

Formal Methods for Functional Verification [chapter]

Randal E. Bryant, James H. Kukula
2003 The Best of ICCAD  
A notable exception is work at IBM on equivalence checking. They developed programs for internal use that could handle very large combinational circuits.  ...  Further developments [41, 38] have continued in diagnostic methods for combinational equivalence checking. % S ¢ ¡ £ 8 # ( 8 t S | ' $ ) 6 9 8 ( E 2 @ A ' t D S Sequential equivalence checking requires  ... 
doi:10.1007/978-1-4615-0292-0_1 fatcat:t776pq6t7reyffs327dkmonjse
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