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Introductory Paper

Enrico Tronci
2006 International Journal on Software Tools for Technology Transfer (STTT)  
The above situation calls for better and better formal verification techniques at all steps of the design flow.  ...  In fact, notwithstanding an ever decreasing project budget, time to market and product lifetime, designers are faced with an ever increasing system complexity and customer expected quality.  ...  Recent advancements in hardware model checking Hardware model checking technology is used in the standard design flow of many leading industries.  ... 
doi:10.1007/s10009-005-0212-y fatcat:35xnumzg5vdzxozujfc67w5jgi

Executing Model Checking Counterexamples in Simulink

Jire Barnat, Lubo Brim, Jan Beran, Kratochvila, Italo R. Oliveira
2012 2012 Sixth International Symposium on Theoretical Aspects of Software Engineering  
Verification of embedded systems has become increasingly important in many industrial domains.  ...  This work has been conducted within the Artemis project industrial Framework for Embedded Systems Tools (iFEST).  ...  Invariance checking of Simulink/Stateflow automotive system designs using a symbolic model checker is also proposed in [15] .  ... 
doi:10.1109/tase.2012.42 dblp:conf/tase/BarnatBBKO12 fatcat:54kvtppvlrgv5jry6365h2trxu

A methodology for improving reliability of complex systems

Atsushi KATOH, Masataka URAGO, Yoshiaki OHKAMI
2010 Synthesiology English edition  
The methodology is constructed by a bridge method of combining architectural design method in systems engineering standards and model checking, which have already been confirmed to be effective in developing  ...  As a trial, the methodology was applied to develop an industrial robot system. The result demonstrates that the proposed methodology is effective for complex industrial systems.  ...  Model checking is "a verification using models", but it has become a proper noun for the verification method. We will add these points to chapter 1.  ... 
doi:10.5571/syntheng.3.197 fatcat:hupgxyfuqnhhlbgqz6ewax2a4a

Complementary verification of embedded software using ASD and Uppaal

Richard Doornbos, Jozef Hooman, Bernard van Vlimmeren
2012 2012 International Conference on Innovations in Information Technology (IIT)  
To increase the confidence in the correctness of software components, we investigated the use of two complementary formal methods in industrial software development.  ...  The combination of the two tools has been applied in industry on a case study of a camera protection system.  ...  ACKNOWLEDGMENT This work has been carried out as a part of the Condor project at FEI Company under the responsibilities of the Embedded Systems Institute (ESI).  ... 
doi:10.1109/innovations.2012.6207775 fatcat:t4ywhu2w65hhhavneyzj2gto4i

Methodology and system for practical formal verification of reactive hardware [chapter]

Ilan Beer, Shoham Ben-David, Daniel Geist, Raanan Gewirtzman, Michael Yoeli
1994 Lecture Notes in Computer Science  
This system was used in the verification of eight designs.  ...  M/tking formal verification a practicality in industrial environments is still difficult.  ...  Acknowledgements We thank the designers of the Haifa Design Group, whose cooperation contributed to the maturity of both the methodology and the system.  ... 
doi:10.1007/3-540-58179-0_53 fatcat:x6eal3hlmff25kt7a4hakua2uq

DiVer: SAT-Based Model Checking Platform for Verifying Large Scale Systems [chapter]

Malay K Ganai, Aarti Gupta, Pranav Ashar
2005 Lecture Notes in Computer Science  
reduction, SAT-based Unbounded Model Checking and Induction for proofs, Efficient Memory Modeling (EMM) and its combination with PBIA in BMC for verifying embedded memory systems with multiple memories  ...  We present a SAT-based model checking platform (DiVer) based on robust and scalable algorithms that are tightly integrated for verifying large scale industry designs.  ...  We present a SAT-based model checking platform (DiVer) based on robust and scalable algorithms [5-7, 11-17, 20, 21] that are tightly integrated for verifying large scale industry designs.  ... 
doi:10.1007/978-3-540-31980-1_41 fatcat:iim7hvhgyzgovaqisprx2cdl54

RTL validation methodology on high complexity wireless microcontroller using OVM technique for fast time to market

Nurul Zhafirah Muhammad, A. Harun, N.A.M.A. Hambali, S. A. Z. Murad, S. N. Mohyar, M.N. Isa, AB Jambek, Mohamad Halim Abd. Wahid
2017 EPJ Web of Conferences  
In reserve, it is very important to discover bugs at infancy of verification process in (SoC) in order to reduce time consuming and fast time to market for the system.  ...  method yet as an effort for fast time to market for the system.  ...  supported two methods; dynamic verification using simulation and formal using model checking.  ... 
doi:10.1051/epjconf/201716201068 fatcat:ha2hy6gyw5hxdgdpewo3q5py44

Industrial Application of Formal Models Generated from Domain Specific Languages [chapter]

Jozef Hooman
2016 Lecture Notes in Computer Science  
Since DSLs can be used to capture essential domain information at a high level of abstraction, this supports formal verification early in the development process.  ...  We discuss our experiences with this approach in a number of real industrial development projects.  ...  Many thanks goes to all of them for the very pleasant collaboration. The anonymous reviewers are acknowledged for several useful comments.  ... 
doi:10.1007/978-3-319-30734-3_19 fatcat:iuy5uuitojahnmghd6kxwounee

Analog Circuit Verification: a State of an Art

Oded Maler
2006 Electronical Notes in Theoretical Computer Science  
Extending formal verification methodology toward analog circuits is a very challenging task that will occupy researchers for some time.  ...  To put this challenge in context we sketch some of the history of digital circuit verification as well as more recent attempts to adapt it to continnuous and hybrid systems.  ...  In simulation/testing (also known as "dynamic verification" in the circuit jargo) a model of the system is used to generate simulation traces, and each of those is checked by the monitor.  ... 
doi:10.1016/j.entcs.2006.02.020 fatcat:ohgm6q37bnbqtlc37nexut5mxy

Formal Verification in a Commercial Settings [chapter]

R. P. Kurshan
2000 Verification of Digital and Hybrid Systems  
This tutorial addresses the following questions: why do formal verification? who is doing it today? what are they doing? how are they doing it? what about the future?  ...  Reduction If we focus on verification as it is practiced today in hardware design industries, then what we see is model-checking.  ...  There is another model for the verification process, in which verification experts dwell on such hard-to-check properties.  ... 
doi:10.1007/978-3-642-59615-5_11 fatcat:hhdf35ivcfg6bkuwhl5zfj2fpq

Analyzing Industrial Architectural Models by Simulation and Model-Checking [chapter]

Raluca Marinescu, Henrik Kaijser, Marius Mikučionis, Cristina Seceleanu, Henrik Lönn, Alexandre David
2015 Communications in Computer and Information Science  
design needs: simulation of EAST-ADL functions in Simulink, model-checking EAST-ADL models with timed automata semantics, and statistical model-checking in UPPAAL, applied on an automatically generated  ...  An industrial Brake-by-Wire prototype is the case study on which we show the potential of simulating EAST-ADL models in Simulink, model-checking downscale EAST-ADL models, as well statistical model-checking  ...  Innovation Systems, within the MBAT project.  ... 
doi:10.1007/978-3-319-17581-2_13 fatcat:r55dndam7rbj3kbgoqdmruzzca

Branching vs. Linear Time: Final Showdown [chapter]

Moshe Y. Vardi
2001 Lecture Notes in Computer Science  
On the other hand, while model checking for CTL can be done in time that is linear in the size of the specification, it takes time that is exponential in the specification for LTL.  ...  Because of these arguments, and for historical reasons, the dominant temporal specification language in industrial use is CTL.  ...  Formal verification, in contrast, uses mathematical techniques to check the entire state space of the design for conformance to some specified behavior.  ... 
doi:10.1007/3-540-45319-9_1 fatcat:2i2vgpeuzfabtj66rylhspbn5y

Model Checking: Back and Forth between Hardware and Software [chapter]

Edmund Clarke, Anubhav Gupta, Himanshu Jain, Helmut Veith
2008 Lecture Notes in Computer Science  
Originally intended for the analysis of concurrent software, model checking was first used in hardware verification.  ...  software in embedded systems.  ...  Model checking was originally designed for the verification of finite state systems.  ... 
doi:10.1007/978-3-540-69149-5_27 fatcat:42jggsgsqzajxflkckzi4wan2i

Preface: Special section on formal methods for industrial critical systems (Selected papers from FMICS'11)

Gwen Salaün, Bernhard Schätz
2014 Science of Computer Programming  
on Formal Methods for Industrial Critical Systems (FMICS'11) .  ...  controllers that were industrially designed using the SCADE Suite.  ... 
doi:10.1016/j.scico.2013.01.008 fatcat:ob4ejmhzpfb27g4dvqvblx2v7y

A Methodology for Developing a Verifiable Aircraft Engine Controller from Formal Requirements [article]

Matt Luckcuck, Marie Farrell, Oisín Sheridan, Rosemary Monahan
2021 arXiv   pre-print
of aerospace systems modelled in Simulink, from the requirements phase through to execution.  ...  In this paper, we present a formal requirements-driven methodology, applied to a model of an aircraft engine controller that has been provided by our industrial partner.  ...  Related work focuses on the verification of a sensor voting module used in the landing gear system using model-checking with Asmeta [3] .  ... 
arXiv:2110.09277v1 fatcat:lu72my5nezg6ddtgsjmafhwfty
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