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Heterogeneous chip multiprocessors

R. Kumar, D.M. Tullsen, N.P. Jouppi, P. Ranganathan
2005 Computer  
Much research remains to be done on the best types and degrees of heterogeneity. However, the advantages of heterogeneous CMPs for both throughput and power have been demonstrated conclusively.  ...  We believe that once homogeneous CMPs reach a total of four cores, the benefits of heterogeneity will outweigh the benefits of additional homogeneous cores in many applications. I  ...  POWER ADVANTAGES Using single-ISA heterogeneous CMPs can significantly reduce processor power dissipation.  ... 
doi:10.1109/mc.2005.379 fatcat:mc2qhtn5yzg2blynpmie2jeuja

Energy efficient job scheduling in single-ISA heterogeneous chip-multiprocessors

Ying Zhang, Lide Duan, Bin Li, Lu Peng, Srinivasan Sadagopan
2014 Fifteenth International Symposium on Quality Electronic Design  
In recent years, single-ISA heterogeneous chip multiprocessors (CMP) consisting of big high-performance cores and small power-saving cores on the same die have been proposed for the exploration of high  ...  In this work, we pay attention to reducing the energy consumption for workloads running on heterogeneous CMPs and propose a scheduling algorithm based on dynamic execution behaviors to exploit better energy-efficiency  ...  [7] introduce a scheduling mechanism to save energy on asymmetric multiprocessors for scientific applications.  ... 
doi:10.1109/isqed.2014.6783390 dblp:conf/isqed/ZhangDLPS14 fatcat:dvqmwnjbmjajhjala7xwruk3v4

An analysis of power reduction in datacenters using heterogeneous chip multiprocessors

Vishal Gupta, Ripal Nathuji, Karsten Schwan
2011 Performance Evaluation Review  
Specifically, we define three use cases of heterogeneous processors for datacenter applications and adopt an analytical approach to quantify relative energy savings of using heterogeneous processors over  ...  Power and design constraints have forced the semiconductor industry to look at alternate solutions like heterogeneous chip multiprocessors to continue application performance scaling and improve energy  ...  We denote such single-ISA heterogeneous CMPs as asymmetric multicore processors (AMPs) as shown in Figure 1b .  ... 
doi:10.1145/2160803.2160867 fatcat:hls2sxh6vncvpgfhlmjwbe7g34

A Survey of Techniques for Architecting and Managing Asymmetric Multicore Processors

Sparsh Mittal
2016 ACM Computing Surveys  
To meet the needs of diverse range of workloads, asymmetric multicore processors (AMPs) have been proposed, which feature cores of different microarchitecture or ISAs.  ...  We hope that more than just synthesizing the existing work on AMPs, the contribution of this survey will be to spark novel ideas for architecting future AMPs that can make a definite impact on the landscape  ...  Also note that most works reviewed in this survey discuss single-ISA AMPs, where all the cores use the same ISA and such systems are specifically termed as asymmetric single-ISA CMP (ASISA-CMP) ].  ... 
doi:10.1145/2856125 fatcat:3hda47vtl5fznfvbskwcm2cbo4

Cross-architecture prediction based scheduling for energy efficient execution on single-ISA heterogeneous chip-multiprocessors

Ying Zhang, Lide Duan, Bin Li, Lu Peng, Srinivasan Sadagopan
2015 Microprocessors and microsystems  
In recent years, single-ISA heterogeneous chip multiprocessors (CMP) consisting of big high-performance cores and small power-saving cores on the same die have been proposed for the exploration of high  ...  In this work, we pay attention to reducing the energy consumption for workloads running on heterogeneous CMPs and propose a scheduling algorithm based on dynamic execution behaviors to exploit better energy-efficiency  ...  They propose an algorithm named HASS [27] to guide the job assignment on single-ISA heterogeneous systems for the maximum performance.  ... 
doi:10.1016/j.micpro.2015.04.008 fatcat:2prvl73am5ezdpphe6g7phrnna

Power-performance efficiency of asymmetric multiprocessors for multi-threaded scientific applications

R.E. Grant, A. Afsahi
2006 Proceedings 20th IEEE International Parallel & Distributed Processing Symposium  
Prototyping AMPs on a commercial 4-way SMP server, we show that on average 15.6% energy savings and 6.1% slowdown for the HT-disabled case, and 7.1% energy savings and 4.8% slowdown for the HT-enabled  ...  An AMP is a multiprocessor system in which its processors are not operating at the same frequency.  ...  Acknowledgments The authors would like to thank the anonymous referees for their insightful comments.  ... 
doi:10.1109/ipdps.2006.1639601 dblp:conf/ipps/GrantA06 fatcat:bbmlbtjf7rakdkfnh65ibrctyi

Survey of Energy-Cognizant Scheduling Techniques

Sergey Zhuravlev, Juan Carlos Saez, Sergey Blagodurov, Alexandra Fedorova, Manuel Prieto
2013 IEEE Transactions on Parallel and Distributed Systems  
Herein we survey the vast field of research on energy-cognizant schedulers. We discuss scheduling techniques to perform energy-efficient computation.  ...  In fact explicitly sacrificing raw performance in exchange for energy savings is becoming a common trend in environments ranging from large server farms attempting to minimize cooling costs to mobile devices  ...  Explicitly asymmetric systems are also referred to as single-ISA heterogeneous systems.  ... 
doi:10.1109/tpds.2012.20 fatcat:jmqqacuxzba47dpatf475ksoti

Guest Editors' Introduction: Interaction of Many-Core Computer Architecture and Operating Systems

Sangyeun Cho, Tao Li, Onur Mutlu
2008 IEEE Micro  
''Using Asymmetric Single-ISA CMPs to Save Energy on Operating Systems,'' by Mogul et al., proposes the use of performance-asymmetric multicore systems in which some cores are specialized to execute operating  ...  of asymmetric multicore processors to save energy in system software, system performance metrics, and operating system improvements to achieve higher throughput in existing multicore systems.  ... 
doi:10.1109/mm.2008.39 fatcat:v74yt5jbxbe55addifn6onsyka

Improving energy efficiency of asymmetric chip multithreaded multiprocessors through reduced OS noise scheduling

Ryan E. Grant, Ahmad Afsahi
2009 Concurrency and Computation  
AMP, a form of single-ISA heterogeneous architecture [17], is a system made up of multiple processors that are not operating at the same speed.  ...  for operating system tasks only and scales its frequency in order to save power, while running user threads on the remaining cores at maximum frequency.  ...  CMPs contain multiple cores on a single chip allowing more than one thread to be executed at a time. Each core has its own resources as well as shared resources, such as the memory bus.  ... 
doi:10.1002/cpe.1454 fatcat:hw64e7tybjhzlfpcvl3nmusi4i

Dynamic power management techniques in multi-core architectures: A survey study

Khaled M. Attia, Mostafa A. El-Hosseini, Hesham A. Ali
2017 Ain Shams Engineering Journal  
However, power management is one of the most critical issues in the design of today's microprocessors. The goal of power management is to maximize performance within a given power budget.  ...  The main objective of this paper is to survey and discuss the current power management techniques.  ...  Using DVFS in asymmetric cores is very popular and can be used in both single-ISA and multiple-ISA heterogeneous architectures [32] .  ... 
doi:10.1016/j.asej.2015.08.010 fatcat:rrzuau4tnzfftngx2rfxatmqom

A study on performance benefits of core morphing in an asymmetric multicore processor

Anup Das, Rance Rodrigues, Israel Koren, Sandip Kundu
2010 2010 IEEE International Conference on Computer Design  
are run, for some percentage of time, on the single morphed core.  ...  We consider as an example a dual core processor with one of the two cores being designed to target integer intensive applications while the other is better suited to floating-point intensive applications  ...  Energy related benefits have also been explored in [1] , where single ISA heterogeneous cores working at different frequencies are used.  ... 
doi:10.1109/iccd.2010.5647566 dblp:conf/iccd/DasRKK10 fatcat:lbyd5nqgbzejhnbb35n3legfmy

Energy Efficient Multi-Core Processing

Charles Leech, Tom J. Kazmierski
2014 Electronics  
concept of minimal architecture synthesis and how it can be used to produce an application specific, energy efficient processor.  ...  Due to the relationship between logic gate count and power consumption, energy efficiency is also maximised in the processor therefore the system is designed to perform a specific task in the most efficient  ...  ACKNOWLEDGMENT This work was supported by the Engineering and Physical Sciences Research Council (EPSRC), UK under grant number EP/K034448/1 " PRiME: Power-efficient, Reliable, Many-core Embedded systems  ... 
doi:10.7251/els1418003l fatcat:ehztmbwggvayddswnnp6qxg2ra

Enabling Network Security in HPC Systems Using Heterogeneous CMPs [chapter]

Ozcan Ozturk, Suleyman Tosun
2014 High-Performance Computing on Complex Environments  
Edited by Emmanuel Jeannot and Julius Žilinskas. 383 384 ENABLING NETWORK SECURITY IN HPC SYSTEMS USING HETEROGENEOUS CMPS distributions that can reduce the energy consumption of the system.  ...  Performance improvements brought by multicore architectures have already been used in network security processors either using homogeneous chip multiprocessors (CMP) or through custom system-on-a-chip  ...  ACKNOWLEDGMENTS This work was supported in part by Open European Network for High-Performance Computing on Complex Environments, the TUBITAK Grant 112E360, and a grant from Turk Telekom under Grant 3015  ... 
doi:10.1002/9781118711897.ch20 fatcat:apzx5plqi5cfhcfv5bise7fcbu

Design of a custom VEE core in a chip multiprocessor

Dan Upton, Kim Hazelwood
2010 2010 IEEE 8th Symposium on Application Specific Processors (SASP)  
We then show that running the VEE on our specialized core uses up to 15% less power per cycle and up to 5% less energy overall than running the same VEE on a general-purpose core.  ...  We use Pin, a widelyused dynamic binary instrumentation system, as a representative process-level VEE.  ...  The VEE core achieves up to 15% savings per-cycle and up to 5% in total energy. Instruction cache conflicts cause more slowdown in crafty, causing it to use more energy in this study.  ... 
doi:10.1109/sasp.2010.5521138 dblp:conf/sasp/UptonH10 fatcat:le7roakzpvfnxkipzgl2a5nks4

The design and implementation of heterogeneous multicore systems for energy-efficient speculative thread execution

Yangchun Luo, Wei-Chung Hsu, Antonia Zhai
2013 ACM Transactions on Architecture and Code Optimization (TACO)  
In the context of Thread-Level Speculation, we demonstrated that on a same-ISA heterogeneous multicore system, by dynamically deciding how on-chip resources are utilized, speculative threads can achieve  ...  To match program execution with the most energy-efficient processor configuration, the system was equipped with a dynamic resource allocation scheme that characterizes program behaviors using novel processor  ...  This work is based on a homogeneous CMP system and does not consider energy consumptions.  ... 
doi:10.1145/2541228.2541233 fatcat:ek4cfgfxxzhprgdytcx6peg3ni
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