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CEDA Currents

2014 IEEE design & test  
A distinguishing feature of a parameter variation is the temporal characteristic. A static parameter variation results from variability in the manufacturing process.  ...  These three designs mitigate the FCLK and V CC guard bands for dynamic parameter variations to enhance microprocessor performance and energy efficiency while providing unique trade-offs in guard band reduction  ...  These three designs mitigate the FCLK and V CC guard bands for dynamic parameter variations to enhance microprocessor performance and energy efficiency while providing unique trade-offs in guard band reduction  ... 
doi:10.1109/mdat.2014.2349276 fatcat:dizsilgpiverlngpl4p5dv3wry

Variation-tolerant circuits: circuit solutions and techniques

J. Tschanz, K. Bowman, V. De
2005 Proceedings. 42nd Design Automation Conference, 2005.  
This paper describes several circuit techniques that can be employed to ensure efficient circuit operation in the presence of ever-increasing variations.  ...  Variation-tolerant circuits and post-silicon tuning techniques are important for minimizing the impacts of these variations.  ...  It is possible to use supply voltage as a method of reducing the impacts of process variations as well.  ... 
doi:10.1109/dac.2005.193915 fatcat:aip7oykevjho5pzpj4ynvpzeki

Variation-tolerant circuits

Jim Tschanz, Keith Bowman, Vivek De
2005 Proceedings of the 42nd annual conference on Design automation - DAC '05  
This paper describes several circuit techniques that can be employed to ensure efficient circuit operation in the presence of ever-increasing variations.  ...  Variation-tolerant circuits and post-silicon tuning techniques are important for minimizing the impacts of these variations.  ...  It is possible to use supply voltage as a method of reducing the impacts of process variations as well.  ... 
doi:10.1145/1065579.1065780 dblp:conf/dac/TschanzBD05 fatcat:m4fv5d7cbzhavkx4kfb7af5wzi

Parameter variations and impact on circuits and microarchitecture

Shekhar Borkar, Tanay Karnik, Siva Narendra, Jim Tschanz, Ali Keshavarzi, Vivek De
2003 Proceedings of the 40th conference on Design automation - DAC '03  
Parameter variation in scaled technologies beyond 90nm will pose a major challenge for design of future high performance microprocessors.  ...  In this paper, we discuss process, voltage and temperature variations; and their impact on circuit and microarchitecture.  ...  INTRODUCTION Systematic and random variations in process, supply voltage and temperature (P, V, T) are posing a major challenge to the future high performance microprocessor design [1, 2] .  ... 
doi:10.1145/775832.775920 dblp:conf/dac/BorkarKNTKD03 fatcat:fkwbpgq5ifhe3iedlxgyprjkra

Parameter variations and impact on circuits and microarchitecture

Shekhar Borkar, Tanay Karnik, Siva Narendra, Jim Tschanz, Ali Keshavarzi, Vivek De
2003 Proceedings of the 40th conference on Design automation - DAC '03  
Parameter variation in scaled technologies beyond 90nm will pose a major challenge for design of future high performance microprocessors.  ...  In this paper, we discuss process, voltage and temperature variations; and their impact on circuit and microarchitecture.  ...  INTRODUCTION Systematic and random variations in process, supply voltage and temperature (P, V, T) are posing a major challenge to the future high performance microprocessor design [1, 2] .  ... 
doi:10.1145/775919.775920 fatcat:7uslxwcxgredxnhmt5foitlpfq

Guest Editors' Introduction: Process Variation and Stochastic Design and Test

T.M. Mak, Sani Nassif
2006 IEEE Design & Test of Computers  
The fourth article, "Using Adaptive Circuits to Mitigate Process Variations in a Microprocessor Design," by Eric Fetzer, is a case study of the Montecito processor (a member of the Itanium processor family  ...  ) and its use of adaptive circuits to combat process variation.  ... 
doi:10.1109/mdt.2006.147 fatcat:uoa6tglnavat3lwn7sacq2jmwa

A survey of cross-layer power-reliability tradeoffs in multi and many core systems-on-chip

Ahmed A. Eltawil, Michael Engel, Bibiche Geuskens, Amin Khajeh Djahromi, Fadi J. Kurdahi, Peter Marwedel, Smail Niar, Mazen A.R. Saghir
2013 Microprocessors and microsystems  
In order to do so, it is crucial to understand the close interplay between the different layers of a system: technology, platform, and application.  ...  As systems-on-chip increase in complexity, the underlying technology presents us with significant challenges due to increased power consumption as well as decreased reliability.  ...  In this section, we survey recent circuit and micro architectural techniques that microprocessor designers are using to mitigate the effects of hard and soft errors.  ... 
doi:10.1016/j.micpro.2013.07.008 fatcat:bl2v6dfvxnfxnble4pkcg2pcw4

Robust and resilient designs from the bottom-up: Technology, CAD, circuit, and system issues

Vijay Janapa Reddi, David Z. Pan, Sani R. Nassif, Keith A. Bowman
2012 17th Asia and South Pacific Design Automation Conference  
In this paper, we describe an interdisciplinary effort toward robust and resilient designs that mitigate the effects of device and circuit parameter variations in order to enhance system performance, energy  ...  The primary cause of this challenge is device and circuit parameter variability, which results from the manufacturing process and system operation.  ...  RESILIENT CIRCUIT DESIGN Circuit designers work with process technology and CAD in order to gain a more accurate understanding of the variation sources and the impact of these variations on circuit performance  ... 
doi:10.1109/aspdac.2012.6165064 dblp:conf/aspdac/ReddiPNB12 fatcat:khckyzmudvc6xfx2lgclvhioke

Design and test strategies for microarchitectural post-fabrication tuning

Xiaoyao Liang, Benjamin C. Lee, Gu-Yeon Wei, David Brooks
2009 2009 IEEE International Conference on Computer Design  
This framework uses on-chip canary circuits to capture systematic variation while using statistical analysis to estimate random variation.  ...  Tuning techniques are capable of adapting the microarchitecture to mitigate the impact of variations at post-fabrication testing time.  ...  Thus, strategies to mitigate process variations often include a post-fabrication component. Post-fabrication tuning configures a chip to compensate for realized process variations.  ... 
doi:10.1109/iccd.2009.5413170 dblp:conf/iccd/LiangLWB09 fatcat:zmqfw7iflndzzbqu3x5s6fr4cm

Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors

D. Brooks, R.P. Dick, R. Joseph, Li Shang
2007 IEEE Micro  
Acknowledgments This work was supported in part by the US National Science Foundation under awards CCF-0048313 and CNS-0347941, in part by Intel, in part by IBM, and in part by the Natural Sciences and  ...  Several researchers have assumed that microprocessor fault processes are Poisson processes and have used exponential distributions to model them.  ...  Process variation greatly influences the other power-related integrated circuit (IC) characteristics explained in this article.  ... 
doi:10.1109/mm.2007.58 fatcat:gebuecbksrgthitqhcvrd2mp2e

Dependable Multicore Architectures at Nanoscale: The View From Europe

Marco Ottavi, Salvatore Pontarelli, Dimitris Gizopoulos, Cristiana Bolchini, Maria K. Michael, Lorena Anghel, Mehdi Tahoori, Antonis Paschalis, Pedro Reviriego, Oliver Bringmann, Viacheslav Izosimov, Hans Manhaeve (+2 others)
2015 IEEE design & test  
Aging (temporal variation), leads to variation in behavior of a circuit over its lifetime, t > 0.  ...  Process variation is the variation of transistor physical parameters due to uncertainties during fabrication process. This type of variation leads to significant performance variation at time t ¼ 0.  ... 
doi:10.1109/mdat.2014.2359572 fatcat:auzazbmvnjd7bebektn53aptje

A case for exploiting complex arithmetic circuits towards performance yield enhancement

Shingo Watanabe, Masanori Hashimoto, Toshinori Sato
2009 2009 10th International Symposium on Quality of Electronic Design  
As semiconductor technologies are aggressively advanced, the problem of parameter variations is emerging. Process variations in transistors affect circuit delay, resulting in serious yield loss.  ...  This paper investigates to exploit the statistical features in circuit delay and to cascade dependent instructions for reducing variations.  ...  In order to mitigate the variability in circuit delay, the use of instruction cascading is proposed by exploiting the statistical feature of circuit delay.  ... 
doi:10.1109/isqed.2009.4810328 dblp:conf/isqed/WatanabeHS09 fatcat:a4jqa3xvj5cbncwkqdk6hf4l2m

Design of a soft-error robust microprocessor

Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis
2009 Microelectronics Journal  
By using the TR+CWSP scheme, timing faults will be mitigated whether they provoke enlargements of the delays of circuit paths at a maximum time variation up to D Delay_Block .  ...  Furthermore, it shows the design steps from the microprocessor RT-level descriptions up to the GDSII stream files that are used to specify the physical design characteristics in an IC manufacture process  ...  Fault Injection by Simulation Fault injection experiments were performed through the post-layout gate-level simulation discussed in section 5.1.1. The goal of this simulation experiment is to verify  ... 
doi:10.1016/j.mejo.2008.10.001 fatcat:pfqera6sdnbshgwa3n7ptqh76u

A Process-Variation-Tolerant Floating-Point Unit with Voltage Interpolation and Variable Latency

Xiaoyao Liang, David Brooks, Gu-Yeon Wei
2008 Digest of technical papers / IEEE International Solid-State Circuits Conference  
These techniques are applied to a single-precision floating-point unit (FPU) designed using a standard CAD synthesis flow in a 0.13µm CMOS logic process with 8 metal layers.  ...  However, under process variation, the delay of critical paths may vary, and a large number of critical paths in circuits reduces the maximum operating frequency of pipelined processors.  ...  Hempstead for help in testing and UMC for chip fabrication.  ... 
doi:10.1109/isscc.2008.4523228 dblp:conf/isscc/LiangBW08 fatcat:arzyakh7srbg5hrxq2uf2npmjq

Leakage and process variation effects in current testing on future CMOS circuits

A. Keshavarzi, J.W. Tschanz, S. Narendra, V. De, W.R. Daasch, K. Roy, M. Sachdev, C.F. Hawkins
2002 IEEE Design & Test of Computers  
These continual scaling requirements pose several technology, circuit design, and testing challenges. Controlling process variation and leakage has become criti-cal in designing and testing ICs.  ...  Leakage averaging and variance Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits Defect-Oriented Testing in the Deep-Submicron Era 36 Barriers to technology scaling, such  ...  Defect-Oriented Testing in the Deep-Submicron Era  ... 
doi:10.1109/mdt.2002.1033790 fatcat:c73dysme2rauxcsllzx35kkdty
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