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Understanding idle behavior and power gating mechanisms in the context of modern benchmarks on CPU-GPU Integrated systems

Manish Arora, Srilatha Manne, Indrani Paul, Nuwan Jayasena, Dean M. Tullsen
2015 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)  
This paper presents a comprehensive analysis of idleness behavior of modern CPU workloads, consisting of both consumer and CPU-GPU benchmarks.  ...  Overall energy consumption in modern computing systems is significantly impacted by idle power. Power gating, also known as C6, is an effective mechanism to reduce idle power.  ...  Fig. 4 : 4 CPU behavior and steps in clock gated vs. power gated state. Fig. 5 . 5 Note that the power shown in the figure is the combined power of the CPU and on-chip GPU.  ... 
doi:10.1109/hpca.2015.7056047 dblp:conf/hpca/AroraMPJT15 fatcat:3glzawrv2fh3dpaba44bhgxrum

Power Consumption by Video Applications [chapter]

Shahriar Akramullah
2014 Digital Video Concepts, Methods, and Metrics  
Therefore, we first introduce the concept of power consumption and view its limits on typical modern devices, then we follow with a discussion of common media workloads and usages on consumer platforms  ...  Power consumption needs to be considered together with those other dimensions; tradeoffs are often made in favor of tuning one of these dimensions, based on the needs of the application and with a view  ...  Understanding why the frequent transitions are happening may help point to power-related issues or improvement prospects. • GPU Power: On the modern processors, as most media applications run on the GPU  ... 
doi:10.1007/978-1-4302-6713-3_6 fatcat:6qnm3xbu3nbr3pmyqou37cnr4e

Evaluation of DVFS techniques on modern HPC processors and accelerators for energy-aware applications

Enrico Calore, Alessandro Gabbana, Sebastiano Fabio Schifano, Raffaele Tripiccione
2017 Concurrency and Computation  
We run selected kernels and a full HPC application on two high-end processors widely used in the HPC context, namely an NVIDIA K80 GPU and an Intel Haswell CPU.  ...  In this work we evaluate, from an user perspective, the use of Dynamic Voltage and Frequency Scaling (DVFS) techniques, assisted by the power and energy monitoring capabilities of modern processors in  ...  Acknowledgements This work was done in the framework of the COKA, COSA and Suma projects of INFN. We would like to thank all developers of the PAPI library (and especially V. M.  ... 
doi:10.1002/cpe.4143 fatcat:qs7g3m2jafgrzkhmaqfc4ioafy

Energy Efficient Computing Systems: Architectures, Abstractions and Modeling to Techniques and Standards [article]

Rajeev Muralidhar and Renata Borovica-Gajic and Rajkumar Buyya
2020 arXiv   pre-print
the power intent or properties at different layers (b) modeling and simulation of the entire system or subsystem (hardware or software or both) so as to be able to perform what-if analysis, (c) techniques  ...  Somewhat in parallel, the semiconductor industry has developed techniques and standards around specification, modeling and verification of complex chips; these areas have not been addressed in detail by  ...  Some systems use an integrated power and performance prediction system to save energy in GPUs.  ... 
arXiv:2007.09976v2 fatcat:enrfj2qgerhyteapwykxcb5pni

Mobile CPU's rise to power: Quantifying the impact of generational mobile CPU design trends on performance, energy, and user satisfaction

Matthew Halpern, Yuhao Zhu, Vijay Janapa Reddi
2016 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)  
Our results quantitatively demonstrate that CPUs play a crucial role in modern mobile system-on-chips (SoCs).  ...  In this paper, we assess the past, present, and future of mobile CPU design. We study how mobile CPU designs trends have impacted the end-user, hardware design, and the holistic mobile device.  ...  Acknowledgements We would like to thank all of the people who have provided comments and suggestions.  ... 
doi:10.1109/hpca.2016.7446054 dblp:conf/hpca/HalpernZR16 fatcat:dcuenxqyljb4bpxijmotq4ugr4

Automated OS-level Device Runtime Power Management

Chao Xu, Felix Xiaozhu Lin, Yuyang Wang, Lin Zhong
2015 SIGARCH Computer Architecture News  
Non-CPU devices on a modern system-on-a-chip (SoC), ranging from accelerators to I/O controllers, account for a significant portion of the chip area.  ...  Based on the observations of existing drivers and their evolution, we consider it harmful to rely on drivers for device runtime PM.  ...  Acknowledgments The work was supported in part by NSF Awards #1054693, #1065506, and #1218041.  ... 
doi:10.1145/2786763.2694360 fatcat:ikn5lu7msvcmhjkrbxgi76vdma

Automated OS-level Device Runtime Power Management

Chao Xu, Felix Xiaozhu Lin, Yuyang Wang, Lin Zhong
2015 Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS '15  
Non-CPU devices on a modern system-on-a-chip (SoC), ranging from accelerators to I/O controllers, account for a significant portion of the chip area.  ...  Based on the observations of existing drivers and their evolution, we consider it harmful to rely on drivers for device runtime PM.  ...  Acknowledgments The work was supported in part by NSF Awards #1054693, #1065506, and #1218041.  ... 
doi:10.1145/2694344.2694360 dblp:conf/asplos/XuLWZ15 fatcat:ddkauzd5inaptclyuksaxkpybe

Automated OS-level Device Runtime Power Management

Chao Xu, Felix Xiaozhu Lin, Yuyang Wang, Lin Zhong
2015 SIGPLAN notices  
Non-CPU devices on a modern system-on-a-chip (SoC), ranging from accelerators to I/O controllers, account for a significant portion of the chip area.  ...  Based on the observations of existing drivers and their evolution, we consider it harmful to rely on drivers for device runtime PM.  ...  Acknowledgments The work was supported in part by NSF Awards #1054693, #1065506, and #1218041.  ... 
doi:10.1145/2775054.2694360 fatcat:dpcpgh363rbx5kxrrxg5j4qy4e

COMPASS

Dong Hyuk Woo, Hsien-Hsin S. Lee
2010 Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems - ASPLOS '10  
However, given such a system-on-chip, the GPU, while occupying a substantial part of the silicon, will sit idle and contribute nothing to the overall system performance when running non-graphics workloads  ...  In this paper, we propose COMPASS, a compute shader-assisted data prefetching scheme, to leverage the GPU resource for improving single-threaded performance on an integrated system.  ...  The authors would also like to thank Ahmad Sharif for his constructive comments on the early version of this paper.  ... 
doi:10.1145/1736020.1736054 dblp:conf/asplos/WooL10 fatcat:io6ezoyhkzcf5jvxeedn57x43e

COMPASS

Dong Hyuk Woo, Hsien-Hsin S. Lee
2010 SIGARCH Computer Architecture News  
However, given such a system-on-chip, the GPU, while occupying a substantial part of the silicon, will sit idle and contribute nothing to the overall system performance when running non-graphics workloads  ...  In this paper, we propose COMPASS, a compute shader-assisted data prefetching scheme, to leverage the GPU resource for improving single-threaded performance on an integrated system.  ...  The authors would also like to thank Ahmad Sharif for his constructive comments on the early version of this paper.  ... 
doi:10.1145/1735970.1736054 fatcat:jdzqcfiov5gvtouq3n623hdgfu

COMPASS

Dong Hyuk Woo, Hsien-Hsin S. Lee
2010 SIGPLAN notices  
However, given such a system-on-chip, the GPU, while occupying a substantial part of the silicon, will sit idle and contribute nothing to the overall system performance when running non-graphics workloads  ...  In this paper, we propose COMPASS, a compute shader-assisted data prefetching scheme, to leverage the GPU resource for improving single-threaded performance on an integrated system.  ...  The authors would also like to thank Ahmad Sharif for his constructive comments on the early version of this paper.  ... 
doi:10.1145/1735971.1736054 fatcat:qwrsaud46jfczphyzo5gzych3a

Exploring weak scalability for FEM calculations on a GPU-enhanced cluster

Dominik Göddeke, Robert Strzodka, Jamaludin Mohd-Yusof, Patrick McCormick, Sven H.M. Buijssen, Matthias Grajewski, Stefan Turek
2007 Parallel Computing  
The first part of this paper surveys co-processor approaches for commodity based clusters in general, not only with respect to raw performance, but also in view of their system integration and power consumption  ...  Thus, even the addition of low-end, out of date GPUs leads to improvements in both performance-and power-related metrics.  ...  Thanks to NVIDIA and ATI for donating hardware that was used in developing the serial version of the GPU backend, and thanks to Mark Harris and Mike Houston for clarifying hardware details.  ... 
doi:10.1016/j.parco.2007.09.002 fatcat:s7z3hudamjds5bxbebsdzkmyb4

Data Center Energy Consumption Modeling: A Survey

Miyuru Dayarathna, Yonggang Wen, Rui Fan
2016 IEEE Communications Surveys and Tutorials  
the entire data center ii) many state-of-the-art power models are based on a few CPU or server metrics, and iii) the effectiveness and accuracy of these power models remain open questions.  ...  , and finally systems of systems level.  ...  The parameters cpu u , γ , δ, σ , cpu f , and P idle represent the CPU utilization, cache miss rate, context switching rate, instructions per cycle, CPU frequency, and idle power dissipation of the system  ... 
doi:10.1109/comst.2015.2481183 fatcat:ne7geca4y5dlbmukdhewsw7p64

D9.3.3: Report on prototypes evaluation

Lennart Johnsson, Gilbert Netzer
2013 Zenodo  
DSPs common for embedded systems and with a TDP about one order of magnitude less than x86 CPUs, the emerging heterogeneous CPUs integrating x86 and GPU cores, and traditional GPUs with a novel direct  ...  Two prototypes focused on novel approaches to scalability of I/O systems in support of Exascale systems and their energy efficiency.  ...  D9.3.3 Report on prototypes evaluation PRACE-1IP -RI-261557 29.03.2013  ... 
doi:10.5281/zenodo.6553033 fatcat:nvxbrlq5jzdfhbkh5fde3kpl4e

Energy Efficiency for Ultrascale Systems: Challenges and Trends from Nesus Project

2015 Supercomputing Frontiers and Innovations  
The analysis contains major areas that are related to studies of energy efficiency in ultrascale systems: heterogeneous and low power hardware architectures, power monitoring at large scale, modeling and  ...  Therefore, this paper presents challenges and trends associated with energy efficiency for ultrascale systems based on current activities of the working group on "Energy Efficiency" in the European COST  ...  ARM Cortex CPUs, and MALI GPU companion, are distributed as system on chip (SoC) design in order to be implemented by external founders but they are free to mix different kind of CPU and GPU cores on chips  ... 
doi:10.14529/jsfi150206 fatcat:uaq7p3nalvb7jb6xnholszwpla
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