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Understanding bug fix patterns in verilog

Sangeetha Sudakrishnan, Janaki Madhavan, E. James Whitehead, Jose Renau
2008 Proceedings of the 2008 international workshop on Mining software repositories - MSR '08  
In this project, we analyze the bug fix history of four hardware projects written in Verilog and manually define 25 bug fix patterns. The frequency of each bug type is then computed for all projects.  ...  We find that 29 − 55% of the bug fix pattern instances in Verilog involve assignment statements, while 18 − 25% are related to if statements.  ...  CHARACTERISTICS OF BUG FIX PATTERNS In this section, we show the frequency of bug fix patterns in the four verilog projects analyzed.  ... 
doi:10.1145/1370750.1370761 dblp:conf/msr/SudakrishnanMWR08 fatcat:mxch6ukxufggncpqu5hxd2djzi

Finding and Understanding Bugs in FPGA Synthesis Tools

Yann Herklotz, John Wickerson
2020 The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays  
Using Verismith, eleven bugs were reported to tool vendors, of which six have already been fixed.  ...  These are implemented in a tool called Verismith. This paper also provides a qualitative and quantitative analysis of the bugs found in Yosys, Vivado, XST and Quartus Prime.  ...  This tool successfully found and reported a total of eleven bugs in Yosys, Vivado and Icarus Verilog, which are now either fixed or confirmed and scheduled to be fixed in upcoming releases.  ... 
doi:10.1145/3373087.3375310 dblp:conf/fpga/HerklotzW20 fatcat:jrvrmtdecza4zhvvhcgfyvhbhi

End-to-End Verification of Processors with ISA-Formal [chapter]

Alastair Reid, Rick Chen, Anastasios Deligiannis, David Gilday, David Hoyes, Will Keen, Ashan Pathirane, Owen Shepherd, Peter Vrabel, Ali Zaidi
2016 Lecture Notes in Computer Science  
This is an end-to-end framework to detect bugs in the datapath, pipeline control and forwarding/stall logic of processors.  ...  The return on investment issues include the need to start catching bugs early in development, the need to continue catching bugs throughout development, and the need to be able to reuse verification IP  ...  As each bug is fixed, we remove the corresponding assumption and confirm that the bug has been fixed.  ... 
doi:10.1007/978-3-319-41540-6_3 fatcat:jaht4ofh4ngblkks2sxs3pujnq

Mining Crash Fix Patterns [article]

Jaechang Nam, Ning Chen
2013 arXiv   pre-print
Our result implies that most of the bugs in software projects can be and should be fixed by only a few common fix patterns.  ...  In order to achieve such goal, in depth studies on the characteristics of bug fixes from well maintained, highly popular software projects are necessary.  ...  Sudhakrishnan et al. analyzed bug fix history of four hardware projects written in Verilog and revealed 25 bug fix patterns [10] .  ... 
arXiv:1311.1895v2 fatcat:qtrvhv6ljfabrmvyw26dk5rp24

Online design bug detection: RTL analysis, flexible mechanisms, and evaluation

Kypros Constantinides, Onur Mutlu, Todd Austin
2008 2008 41st IEEE/ACM International Symposium on Microarchitecture  
First, we analyze the actual design bugs found and fixed in a commercial chipmultiprocessor, Sun's OpenSPARC T1, to understand the behavior and characteristics of design bugs.  ...  Although a large amount of resources and time are devoted to the verification phase of modern processors, many design bugs escape the verification process and slip into processors operating in the field  ...  Test Pattern Generation [14, 28] .  ... 
doi:10.1109/micro.2008.4771798 dblp:conf/micro/ConstantinidesMA08 fatcat:jnaolfr7yvaonm4j62ykpqt3hi

Assertion Based Functional Verification of March Algorithm Based MBIST Controller [article]

Ashwani Kumar
2021 arXiv   pre-print
ABV approach helped to make the verification and design process efficient and less time-consuming by finding the bugs, exercising the corner cases in the design, and using the directed test cases in a  ...  In assertion based functional verification, creation of verification plan, for MBIST controller RTL model and the implementation & simulation of the verification plan using System-Verilog and Synopsys-VCS  ...  These corner cases may keep bugs which can cause the wrong functional behavior of design. In this way ABV helps to finds out the bugs present in the design.  ... 
arXiv:2106.11461v1 fatcat:4q37rfbswrc3fe66logyqlfp2m

Examining Zero-Shot Vulnerability Repair with Large Language Models [article]

Hammond Pearce and Benjamin Tan and Baleegh Ahmad and Ramesh Karri and Brendan Dolan-Gavitt
2022 arXiv   pre-print
Human developers can produce code with cybersecurity bugs. Can emerging 'smart' code completion tools help repair those bugs?  ...  We investigate challenges in the design of prompts that coax LLMs into generating repaired versions of insecure code.  ...  Of the many tasks coders do, we are interested in fixing security bugs; developers might ordinarily run security tools such as fuzzers or static analyzers, try to understand the feedback, locate the issue  ... 
arXiv:2112.02125v3 fatcat:ho3s4ehl5bcobadg3qfqorzwym

A Comparative Study of Chisel for FPGA Design

Paul Lennon, Richard Gahan
2018 2018 29th Irish Signals and Systems Conference (ISSC)  
Each component is implemented with a deep lowlevel hardware understanding with an aim to evaluate the merits of designing with Chisel from a hardware designers' perspective.  ...  The authors discover Chisel's merits for realising synthesizable repetitive designs such as in SoC development, experiencing the benefits of Chisel's object-oriented background in enhancing code maintainability  ...  The number and pattern in which RAM blocks are tiled is based on the dimensions of the FIFO and the dimensions of the target device's RAM blocks.  ... 
doi:10.1109/issc.2018.8585292 fatcat:f5kduwvocbbcvdo37lyejvqnly

A program differencing algorithm for verilog HDL

Adam Duley, Chris Spandikow, Miryung Kim
2010 Proceedings of the IEEE/ACM international conference on Automated software engineering - ASE '10  
To help programmers reason about the differences at a high-level, Vdiff outputs syntactic differences in terms of Verilog-specific change types.  ...  This paper presents Vdiff, an instantiation of this position-independent differencing algorithm for Verilog HDL.  ...  [27] studied the types of bugs that occur in Verilog and compared those findings to a similar study in Java.  ... 
doi:10.1145/1858996.1859093 dblp:conf/kbse/DuleySK10 fatcat:zml5vx7pjjgt3jk4m2vqj2mfm4

Chip multi-processor generator

Alex Solomatnikov, Amin Firoozshahian, Wajahat Qadeer, Ofer Shacham, Kyle Kelley, Zain Asgar, Megan Wachs, Rehan Hameed, Mark Horowitz
2007 Proceedings - Design Automation Conference  
As presented in Chapter 2 of this thesis, the chip generator approach uses a fixed system architecture, or "template," to simplify both software development and hardware verification.  ...  When I met Steve for the first time, he manifested his goal as to "help students understand what they are doing and what they need to do to achieve their PhD goals."  ...  bugs found and fixed.  ... 
doi:10.1145/1278480.1278544 dblp:conf/dac/SolomatnikovFQSKAWHH07 fatcat:r5cfnoxqarg5lghtnmqidi7wxy

xMAS: Quick Formal Modeling of Communication Fabrics to Enable Verification

Satrajit Chatterjee, Michael Kishinevsky, Umit Y. Ogras
2012 IEEE Design & Test of Computers  
In this paper we identify a richer set of microarchitectural primitives that allows us to describe complete systems by composition alone.  ...  However, unlike other formalisms this approach leads to a precise yet intuitive graphical notation for microarchitecture that captures timing and functionality in sufficient detail to be useful for reasoning  ...  To address the verification problem we generate abstract Verilog out of our models and use in-house and academic verification tools for formal bug-hunting by reducing liveness problem to standard safety  ... 
doi:10.1109/mdt.2012.2205998 fatcat:kn7znkz3ind7tolovcg4nowrpy

xMAS: Quick Formal Modeling of Communication Fabrics to Enable Verification

Satrajit Chatterjee, Mike Kishinevsky, Umit Ogras
2013 IEEE design & test  
In this paper we identify a richer set of microarchitectural primitives that allows us to describe complete systems by composition alone.  ...  However, unlike other formalisms this approach leads to a precise yet intuitive graphical notation for microarchitecture that captures timing and functionality in sufficient detail to be useful for reasoning  ...  To address the verification problem we generate abstract Verilog out of our models and use in-house and academic verification tools for formal bug-hunting by reducing liveness problem to standard safety  ... 
doi:10.1109/mdt.2011.72 fatcat:wbhokst7kzgzpnoyilrgwhfdsi

Behavior Driven Development for circuit design and verification

Melanie Diepenbeck, Mathias Soeken, Daniel Grose, Rolf Drechsler
2012 2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)  
In this paper, we propose a new design flow based on Behavior Driven Development (BDD), an agile technique for the development of software in which acceptance tests written in natural language play a central  ...  role and are the starting point in the design flow.  ...  INTRODUCTION With the advent of computers the problems of bugs in hardware and software arose.  ... 
doi:10.1109/hldvt.2012.6418237 dblp:conf/hldvt/DiepenbeckSGD12 fatcat:2k3mm65ntfd6xmls3bodgzldd4

Vdiff: a program differencing algorithm for Verilog hardware description language

Adam Duley, Chris Spandikow, Miryung Kim
2012 Automated Software Engineering : An International Journal  
To help programmers reason about the differences at a high-level, Vdiff outputs syntactic differences in terms of Verilog-specific change types.  ...  This paper presents Vdiff, an instantiation of this position-independent differencing algorithm for Verilog HDL.  ...  Hardware projects are in a constant state of change during the development process due to new feature requests, bug fixes, and demands to meet power reduction and performance requirements.  ... 
doi:10.1007/s10515-012-0107-6 fatcat:m4amwaijbfhxhmehbfjrsyzkuq

Design experience of a chip multiprocessor merlot and expectation to functional verification

Satoshi Matsushita
2002 Proceedings of the 15th international symposium on System Synthesis - ISSS '02  
However, bugs found in later stage of design have required larger manpower or delay of project.  ...  In this paper, we also discuss the methodology to improve functional verification coverage, and expect the solution in formal approaches.  ...  The size of source is reduced to 40% of final verilog RTL (Register Transfer Level) description in words in 168 source files.  ... 
doi:10.1145/581199.581223 fatcat:x36o4c62hbh7vaozjrpgrwzvte
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